Ge Aviation Systems Limited

Sony United Kingdom Limited

Ceramaspeed Limited

Nicholas George Tembe

Peter James Handy

Peter Charles Eastty

Ian David Johnson

Multi-semiconductor SSPCs that solve bus level problems affecting systems as well as controller level problems affecting individual multi-semiconductor SSPCs are disclosed. Bus level and controller level problems adversely affect multi-semiconductor SSPCs and their associated systems. The disclosed multi-semiconductor SSPCs solve both bus level and controller level problems by implementing controlled rate-change of voltage (dv/dt) ramp-on rate, to ensure that the voltage on the input bus does not collapse when a multi-semiconductor SSPC is commanded closed and that a minimum amount of power is being dissipated evenly across the switching semiconductors.

Method and apparatus for DV/DT controlled ramp-on in multi-semiconductor solid-state power controllers

A passive leakage management circuit for a switch leakage current including a switch having operable in a first operating mode, wherein the switch output supplies an output current having a first predetermined voltage, and a second operating mode, wherein the switch output supplies a leakage current having a second voltage, a first current path, and a leakage current path.

Passive leakage management circuit for a switch leakage current

A passive leakage management circuit for a switch leakage current includes a switch being operable in a first operating mode, wherein the switch output supplies an output current having a first predetermined voltage. In a second operating mode, the switch output supplies a leakage current having a second voltage, a first current path, and a leakage current path.

An analog-to-digital conversion arrangement converting an input analog signal into an output digital representation. Two or more analog-to-digital conversion paths each applying a conversion mapping between input analog signal magnitudes and respective digital values generate an intermediate representation of the input analog signal, the conversion paths being operable to apply different respective conversion mappings. An output circuit combines the intermediate representations from at least two conversion paths to generate the output digital representation, the intermediate representations being combined according to a weighting dependent on the magnitude of the input analog signal. At least one of the conversion paths has an enhanced sensitivity mode appropriate to a range of magnitudes of the input signal that are below a threshold magnitude. Control logic inhibits operation in the enhanced sensitivity mode if the magnitude of the input analog signal exceeds the threshold magnitude.

Analogue to digital conversion

In a method and apparatus for controlling an electric cooking appliance, a boost condition is initiated by increasing the power level of one or more electric heating means () to a maximum power level from a previous lower power level. Elapsed time () during cooling of the appliance since an end of an immediately previous period at the maximum power level is monitored, as is difference in power levels between the maximum power level and the previous lower power level. Duration () of the boost condition is set according to one of the elapsed time () and the difference in power levels and a level () of temperature boost in the boost condition is correspondingly set according to one of the difference in power levels and the elapsed time respectively.

Growing community of inventors

Worcester, United Kingdom

Nicholas George Tembe