Lsi Logic Corporation

Other

Lsi Logic Corportion

Nicholas F Pasch

Michael D Rostoker

Joe Zelayeta

Ashok K Kapoor

Nicholas K Eib

Richard D Schinella

Ranko L Scepanovic

Edwin R Jones

Mark R Schneider

Mario Garza

Keith K Chao

Dusan Petranovic

John V Jensen

Colin D Yates

Vahak K Sahakian

Conrad J Dell'Oca

Philippe Schoenborn

Roger Patrick

Shumay X Dou

Thomas G Mallon

Mark A Franklin

Abraham Fong Yee

Rajat Rakkhit

William H Gascoyne

Aldona M Butkus

William C Schneider

Sheldon Aronowitz

Joe W Zhao

Dawn M Lee

Ratan K Choudhury

David J Heine

Richard S Osugi

Ana Ley

Jeffrey Dong

Jayashree Kalpathy Cramer

Glenn C Sanders

Marilyn Hwan

James L Hubbard

The present invention relates to a printer system that incorporates an electrically addressable array of micro electro-mechanical switches of arbitrary width. In one embodiment, array of micro electro-mechanical switches of arbitrary width that comprises an electrostatic array used to attract fusible toner or electrically charged ink droplets from a hopper or ink jet assembly to a piece of paper or other printable substrate. The electrostatic array uses electrostatic latching to create the charged environment to allow the toner or ink to be attracted from the hopper or ink jet assembly toward the array. A piece of paper is interposed between the array and the hopper or ink jet assembly. Additional micro electro-mechanical switches control the release of the ink droplets from the ink jet assembly. The micro electro-mechanical switches each comprise a sealed cell that relies on pneumatic restoration forces to insure that switch contacts can be successfully broken as desired.

Electrostatic printers using micro electro-mechanical switching elements

Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

Automating photolithography in the fabrication of integrated circuits

A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry. In a preferred embodiment, the test pattern formed in each of the selected fields in the first layer comprises a pattern of parallel spaced apart lines, and the latent images formed in the portions of the photoresist layer in the selected fields above the test pattern in the first layer also comprises a pattern of parallel spaced part lines, with the two sets of lines interspaced between one another and generally parallel to one another to form a diffraction pattern.

Alignment process for integrated circuit structures on semiconductor substrate using scatterometry measurements of latent images in spaced apart test fields on substrate

The present invention is a method and apparatus for applying one-dimensional proximity correction to a piece of a mask pattern, by segmenting a first piece of a mask pattern with horizontal dividing lines into a plurality of segments, segmenting a second piece of said mask pattern with said horizontal dividing lines into a second plurality of segments, and applying proximity correction to a first segment from said first plurality of segments taking into consideration a second segment from said second plurality of segments.

Method and apparatus for application of proximity correction with relative segmentation

The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Method and apparatus for application of proximity correction with unitary segmentation

An integrated circuit structure is provided with a local interconnect layer and a first metal interconnect layer which are both capable of bridging over underlying conductive regions. The structure comprises a first dielectric layer formed to a height or thickness equal to or preferably exceeding the height of the highest conductive regions of the underlying integrated circuit devices; a second dielectric layer formed above the first dielectric layer; one or more local interconnects formed in the second dielectric layer; and a thin third dielectric layer formed over the second dielectric layer and the local interconnects therein. The thin third dielectric layer has a thickness not exceeding about 2000 &angst;, and preferably ranging from about 1000 &angst; to about 1500 &angst;. A first layer of metal interconnects is formed over the thin third dielectric layer. Conventionally formed filled contact openings extend from the substrate through the first dielectric layer to either filled vias or a local interconnect in the second dielectric layer. The metal interconnects are electrically connected to either filled vias or one or more local interconnects in the second dielectric layer by filled shallow vias in the thin third dielectric layer. The shallow vias in the thin third dielectric layer are preferably filled with the same metals used to form the first layer of metal interconnects.

Process for making integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level

Increased resolution is available from acid-catalyzed photoresist used in fabricating integrated circuits by inhibiting chemically-basic contaminants from contacting the photoresist placed above an IC structure which emits those chemically-basic contaminants. The inhibition can result from physical barrier characteristics of a barrier layer placed between the contaminant-emitting surface and the overlying layer of photoresist, or the layer of barrier material may contain acid moieties which chemically neutralize the emitted chemically-basic contaminants before the contaminants reach the photoresist.

Method of protecting acid-catalyzed photoresist from chip-generated basic contaminants

A thermally stable inter-metal dielectric for interlayer dielectric material has enhanced adhesiveness by introduction of an adhesive material. The adhesive material may reside only at the interface of the inter-metal dielectric or interlayer dielectric with adjacent metalization and polysilicon layers. A disclosed thermally stable intermetal dielectric is a fluorinated polymer such as polyfluoropyreline. A disclosed adhesive material is a highly polar material such as a thiofluorocarbon. These materials may be deposited by chemical vapor deposition by first activating fluoropyreline monomer and di(thiodifluoromethane) in a heated activation chamber to convert them to a form suitably reactive to form a polymeric dielectric on a wafer surface.

Polymeric dielectric layers having low dielectric constants and improved adhesion to metal lines

The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distance apart to ensure that no proximity effects will occur between elements fully integrated in different cells. A one-dimensional optical proximity correction technique is performed on the mask design by performing proximity correction only on those components, e.g., lines, that are not fully integrated within one cell.

System and method for performing optical proximity correction on the interface between optical proximity corrected cells

Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing. Manufacturing data including process and. yield parameters is then transferred back to the Rayleigh processor for use in the designing of subsequent circuits. In this way, a direct coupling exists between the measurement of wafer process parameters and the automated sizing of semiconductor devices, enabling the production of circuits having the smallest manufacturable device sizes available for the given lithography and wafer process.

An E-beam generator and detector arrangement sends an electron beam through a series of differentially evacuated vacuum chambers of small size to detect faulty circuitry in individual semiconductor devices. The vacuum chambers are open to one end and are sealed by the semiconductor device without contacting the vacuum chambers. A laser generator is operated by a control system with the E-beam generator and detector arrangement to provide a laser beam in a known physical relationship to the electron beam to correct detected faulty circuitry in the semiconductor devices. The E-beam generator and detector arrangement confirms the correction without further handling of the semiconductor device.

Laser fault correction of semiconductor devices

A process of inhibiting a corrosion of metal plugs formed in integrated circuits is described. The corrosion inhibiting process includes providing a partially fabricated integrated circuit surface including the metal plugs on a polishing pad to carry out chemical-mechanical polishing, introducing slurry including a corrosion inhibiting compound on the polishing pad in sufficient concentration to inhibit corrosion of the metal plugs of the partially fabricated integrated circuit surface, and polishing the partially fabricated integrated circuit surface.

Use of corrosion inhibiting compounds to inhibit corrosion of metal plugs in chemical-mechanical polishing

Integrated circuit structure with thin dielectric between at least local interconnect level and first metal interconnect level, and process for making same

Electron beam fault detection of semiconductor devices

The present invention is a method and apparatus for systematically applying proximity corrections to a mask pattern, wherein the pattern is divided into a grid of equally sized grid rectangles, an inner rectangle comprising a plurality of grid rectangles is formed, an outer rectangle comprising a second plurality of grid rectangles and the inner rectangle is formed and proximity correction is applied to the pattern contained within the inner rectangle as a function of the pattern contained within the outer rectangle.

Method and apparatus for general systematic application of proximity correction

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Pacifica, CA, United States of America

Nicholas F Pasch