Intel Corporation

Nicholas E Duresky

Sameer Nanavati

Saurin Shah

Manan Patel

Jonathan W Liu

Sunil B Chaudhari

Corey Gee

Bapi Vinnakota

Sunil C Chaudhari

A method and apparatus for controlling access to a plurality of resources based on multiple received requests is provided. The system includes a priority register configured to receive each individual request, determine a priority for the request, and transmit the request to a priority appropriate path. A first high priority arbiter receives and arbitrates among highest priority requests in a round robin manner to determine a high priority suggested grant vector. At least one lower priority arbiter receiving and arbitrating among lower priority requests in a round robin manner to determine at least one lower priority suggested grant vector. Grant circuitry passes the high priority suggested grant vector unless said grant circuitry receives a low priority indication, whereby the grant circuitry passes a lower priority grant vector.

Multilevel fair priority round robin arbiter

An embodiment of the present invention includes first and second storage elements. The first storage element stores request information transmitted from a first processor operating at a first frequency. The first and second processors operate at different frequencies. The request information is organized according to a request format. The second storage element stores response information transmitted by a second processor operating at a second frequency different than the first frequency in response to the request information. The response information is organized according to a response format.

Asynchronous communication protocol using efficient data transfer formats

A method, apparatus, and system for communicating between a digital signal processor (DSP) and a packet processor.

DSP interface for packet processing

Growing community of inventors

San Jose, CA, United States of America

Nicholas E Duresky