Sun Microsystems, Inc.

Celerity Computing

Nicholas E Aneshansley

Andrew Jackson McCrocklin

Daniel P Drogichen

Patricia Shanahan

Michael Vaughn Konshak

Andrew E Phelps

James E Kocol

Guoping Xu

Gary L Riddle

Jeffrey P Anderson

James J Whelan

Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and hardware isolation from each other. Clusters can share dynamically definable ranges of memory with each other. The domain filter has software-loadable registers on the system units and in the global routers to set the parameters of the domains and clusters. The registers label individual inter-system transactions on the routers as invalid for system units not in the same domain or cluster as the originating unit.

Multiprocessor computer having configurable hardware system domains

A thermal transfer apparatus for cooling a heat-producing electronic component includes an evaporator disposed over the heat-producing electronic component and thermally coupled to the heat-producing electronic component, a plurality of heat pipes carrying a working fluid therein disposed over the evaporator and thermally coupled to the evaporator, a cold plate thermally coupled to a first end of the plurality of heat pipes, and a condenser thermally coupled to a second end of the plurality of heat pipes. The heat pipes extend over the evaporator such that the first end and the second end of the heat pipes couple to the cold plate and condenser at a location not over the heat-producing electronic component. The cold plate and the condenser are supplied with a coolant from outside the thermal transfer apparatus.

Thermal transfer technique using heat pipes with integral rack rails

The present invention provides a method and apparatus for invalidating a victimized entry. The apparatus comprises a directory cache adapted to store one or more cache entries, and a control unit. The control unit is adapted to determine whether it is desirable to remove a shared cache entry from the directory cache, and invalidate the shared cache entry in response to determining that it is desirable to remove the shared cache entry from the directory cache.

Victim invalidation

A direct-execution microprogrammable microprocessor system uses an emulatory microprogrammable microprocessor for direct execution of microinstructions in main memory through a microinstruction port. A microinstruction cache with a microinstruction address extension unit serving to communicate microinstructions from the main memory to the microprogrammable microprocessor. Virtual main memory accesses occur through a system multiplexer. A virtual address extension unit and a virtual address bus provide extension and redefinition of the main memory address space of the microprogrammable microprocessor. The system also uses a context switching stack cache and an expanded address translation cache with the microprogrammable microprocessor having a reduced and redefined microinstruction set with a variable microinstruction cycle.

Direct-execution microprogrammable microprocessor system

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San Diego, CA, United States of America

Nicholas E Aneshansley