Intel Corporation

Digital Equipment Corporation

Other

Nicholas D Wade

Peter D MacWilliams

Rebecca L Stamm

William S Wu

Radhakrishnan Venkataraman

Norman J Rasmussen

Ken M Crocker

Gilbert A Neiger

Brian K Langendorf

Bruce A Young

Kai Cheng

James M Dodd

Raymond L Strouble

Ruth I Bahar

Christopher B Wilkerson

Richard Lee Sites

John H Edmondson

Gary A Solomon

Derrick R Meyer

George R Hayek

Jeffrey L Rabe

Douglas E Sanders

Michael A Callander

Mark Lalich

Abid Asghar

Linda Chao

R Iris Bahar

A method and apparatus for optimizing control on a bank to bank basis of a memory subsystem having a plurality of memory banks which are installed with different types of dynamic random access memory (DRAM) devices is presented. The present invention includes an improved DRAM controller comprises a set of configuration registers which store configuration bits corresponding to each memory bank in the main memory that is populated with the DRAM devices. The memory controller also includes a detection logic which together with a memory bank decode logic enables the memory controller determine whether a particular memory bank is populated with a page mode DRAM or an extended data out DRAM. The preferred embodiment also includes a column address strobe state machine which automatically controls timing requirements of both type of DRAM devices installed in the main memory to quickly and efficiently handle access requests.

Method and apparatus for controlling of a memory subsystem installed with standard page mode memory and an extended data out memory

In some embodiments, a computer system includes nodes connected through conductors to form a ring. Messages are transmitted on the ring and at least some of the nodes each include control circuitry to receive the messages in a node reception order that is different for each node and order the messages in a global order that is the same for each node having the control circuitry.

Passive message ordering on a decentralized ring

In a memory subsystem having a plurality of memory banks populated with up to a corresponding plurality of dynamic random access memory (DRAM) modules, the DRAM modules being of an extended data out type DRAM module or a page mode type DRAM module, ascertaining the type of DRAM module installed in populated ones of the plurality of memory banks. The DRAM type is determined by storing a predetermined value to a predetermined location in populated ones of the plurality of memory banks, and subsequently reading data from the predetermined location of populated ones of the plurality of memory banks using a page read control signal suitable for the extended data out type DRAM modules. If the data read corresponds to the predetermined value stored, an extended data out type DRAM module is identified.

Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics

An LRU with protection method is provided that offers substantial performance benefits over traditional LRU replacement methods by providing solutions to common problems with traditional LRU replacement. By dividing a cache entry list into a filter sublist and a reuse list, population and protection processes can be implemented to reduce associativity and capacity displacement. New cache entries are initially stored in the filter list, and the reuse list is populated with entries promoted from the cache list. Eviction from the filter list and reuse list is done by a protection process that evicts a data entry from the filter, reuse, or global cache list. Many variations of protection and eviction processes are discussed herein, along with the benefits each provides in reducing the effect of unwanted displacement problems present in traditional LRU replacement.

Least recently used replacement method with protection

Memory bus extensions to a high speed peripheral bus are presented. Specifically, sideband signals are used to overlay advanced mechanisms for cache attribute mapping, cache consistency cycles, and dual processor support onto a high speed peripheral bus. In the case of cache attribute mapping, three cache memory attribute signals that have been supported in previous processors and caches are replaced by two cache attribute signals that maintain all the functionality of the three original signals. In the case of cache consistency cycles, advanced modes of operation are presented. These include support of fast writes, the discarding of write back data by a cache for full cache line writes, and read intervention that permits a cache to supply data in response to a memory read. In the case of dual processor support, several new signals and an associated protocol for support of dual processors are presented. Specific support falls into three areas: the extension of snooping to support multiple caches, the support of shared data between the two processors, and the provision of a processor and upgrade arbitration protocol that permits dual processors to share a single grant signal line.

Method and apparatus for sharing a signal line between agents

In some embodiments, a computer system includes nodes connected through conductors. At least some of the nodes each include memory and processing circuitry to receive snoop requests in a node reception order and to initiate snoops of the memory in the node before the snoop requests are in a global order. The at least some nodes also each include an ordering buffer to receive the snoop requests and provide them at an output of the ordering buffer in the global order.

Out-of-order snooping for multiprocessor computer systems

A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.

Method and apparatus for dynamically resizing a frame buffer in a shared

Method and apparatus for dynamically allocating and resizing the

An apparatus and method for connecting a bus bridge to a plurality of bus interfaces are disclosed. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.

Method and apparatus for multiplexing signals from a bus bridge to an

Method and apparartus for sharing a signal line between agents

The shared computer system memory is partitioned between system memory and frame buffer memory. The memory controller and the graphics controller share access to the computer system memory through a single interface bus. An arbitration unit is provided to arbitrate competing usage requests to the memory from the memory controller and the graphics controller. The arbitration unit may form a portion of the memory controller or may be configured as a stand alone unit. In either case, the arbitration unit resolves competing usage requests by applying a prioritization protocol. The arbitration unit grants control of the memory to either the memory controller or the graphics controller depending upon which has asserted a higher priority request. Once the graphics controller has been granted control of the memory, the arbitration unit cannot revoke control from the graphics controller. Rather, the arbitration unit requests that the graphics controller relinquish control. In one embodiment, communication between the arbitration unit and the graphics controller utilizes only two signal lines, a request line and a grant line. A two-wire protocol is disclosed which allows the graphics controller to assert two different levels of priority requests using the single request line. Method and apparatus embodiments of the invention are disclosed.

Method and apparatus for arbitrating access requests to a shared

A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and dedicated memory to be used by one or more devices. A portion of the physical memory is allocated as a dedicated memory for some system device. The remainder of the memory may be allocated as system memory. The allocation is performed by a system BIOS either at initial start up or through system BIOS calls made during initialization of the device to use the dedicated memory. Programmable bits in the chipset are programmed to prevent the memory controller from claiming dedicated memory accesses during the boot of an operating system. Since the operating system's attempts to write to the dedicated memory are not claimed by the memory controller during memory sizing, they are forwarded to an I/O bus. No 1/0 device claims these addresses, so a memory sizing read back is unanswered, and the operating system is caused to believe the top of memory has been reached below the dedicated memory. If the O/S does not do memory sizing, the system BIOS provides the O/S with the size of system memory available. Thus, in either case, the dedicated memory allocation is transparent to the O/S, and an arbitrary O/S may be employed with the system.

Method and apparatus to permit the boot of a shared memory buffer

Apparatus and a method for eliminating deadlock in a multibus computer system which system includes a primary bus, and a secondary bus, a bridge circuit for joining the primary bus to a bus master, and a second bridge circuit for joining the primary bus to the secondary bus. The invention causes the second bridge circuit to generate a first signal directed to the all bridge circuits to indicate that a bus master on the secondary bus desires access to the secondary bus. All bridge circuits holding data directed to a component on the secondary bus flushes all temporary storage means holding data directed to a component on the secondary bus. The bridge circuits then generate signals to indicate that flushing is complete and the bus master on the secondary bus is granted access to the secondary bus. In one embodiment, the second bridge tests to determine whether the bus master requesting access requires a guaranteed access time and generates a signal to flush temporary storage in the first bridge between memory and the bridge.

Deadlock avoidance mechanism and method for multiple bus topology

Scalable cache attributes for an input/output bus

An arbitration signaling mechanism for an intermediate bus coupled between an expansion bridge and a host bridge that manages communication over the intermediate bus. The host bridge includes a CPU posting buffer for posting transactions between a CPU and the expansion bridge, and a DRAM buffer for storing data to be written into the DRAM. The host bridge also includes an arbiter coupled to receive a request signal from the expansion bridge and any other bus agents coupled to the expansion bridge. Responsive to a request from the expansion bridge, the arbiter empties the CPU posting buffer and the DRAM buffer before asserting an acknowledge signal. A passive release method is provided, which includes signaling a passive release semantic by the expansion bridge during a communication cycle in which the expansion bridge has bus control. The host bridge can grant temporary use of the bus to another bus agent before again granting access to the expansion bridge.

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Vancouver, WA, United States of America

Nicholas D Wade