Seagate Technology Incorporated

Nicholas Carl Seroff

William Leon Rugg

Gabriel Ibarra

A data storage device comprises a data storage medium and a connector that provides an interface between the data storage medium and a host device. The connector has a shape that substantially conforms to an internal storage interconnect standard. The connector comprises a first set of electrical contacts that substantially conform to the internal storage interconnect standard, and a second set of contacts configured to provide connectivity with the host device in accordance with an external storage interconnect standard. Also described are cables for connecting the data storage device to a host via the external storage interconnect standard as well as an interconnect detector.

Data storage device compatible with multiple interconnect standards

A data storage device comprises a data storage medium; an interface between the data storage medium and a host device configured to provide connectivity according to a plurality of storage interconnect standards. The data storage device also includes a interconnect detector configured to determine the presence of a physical connection to the host device and identify an interconnect standard of the host device, wherein the interconnect standard of the host device is one of the plurality of storage interconnect standards; and a controller configured to: receive an indication of the interconnect standard of the physical connection from the interconnect detector, receive data access commands in accordance with the interconnect standard from the host device via the connector; process the data access commands by accessing the data storage medium; and send a response to the data access commands in accordance with the interconnect standard to the host via the connector.

An integrated circuit device having a plurality of embedded processor/controllers and a parallel emulation trace port coupled thereto to provide trace data for debugging the integrated circuit device. A serializer macro is provided within the integrated circuit device to serialize the parallel data from the emulation trace port in order to provide trace data from the IC device in a serial data stream instead of a parallel data stream. A high speed differential serial driver is used to provide the bandwidth required to support the data speeds associated with embedded processors running at high clock rates. An external serial to parallel converter is also provided to convert the high speed serial trace data back to parallel trace data such that the trace data can be input into an emulator in the normal manner. In one embodiment, two serializers are provided within the integrated circuit device to meet data throughput requirements, such as when the IC device has more than one embedded processor/controller. Multi-level signaling of the serial data stream is also provided to further enhance throughput/bandwidth capabilities.

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Boulder, CO, United States of America

Nicholas Carl Seroff