Arm Limited

Nicholas Andrew Salter

Ian Victor Devereux

Dipesh Ishwerbhai Patel

Andrew John Sowden

Harry Edward Oldham

A data processing apparatus and method are provided for controlling level shifting. The data processing apparatus comprises a first component provided within a first voltage domain and operable to receive a first supply voltage, and a second component provided within a second voltage domain and operable to receive a second supply voltage. At least one of the first and second supply voltages are dynamically variable. The data processing apparatus further comprises an interface cell between the first and second voltage domains which is operable to receive a signal issued by the first component in the first voltage domain and destined for the second component. The interface cell comprises level shifting logic operable to convert the signal issued by the first component into a corresponding signal to be propagated to the second component in the second voltage domain. Further, bypass logic is provided which is operable in the event that the first supply voltage and second supply voltage are at the same voltage level to enable a bypass path around the level shifting logic such that the signal issued by the first component is propagated via the bypass path as the corresponding signal to the second component in the second voltage domain.

Level shifting in a data processing apparatus

The present invention provides a data processing apparatus for fetching an instruction in to an instruction cache, comprising an instruction cache for storing instructions, and a processor core for outputting an instruction address to the instruction cache on an instruction address bus, and for receiving the instruction corresponding to that instruction address on an instruction data bus The processor core is arranged to issue a predetermined control signal to the instruction cache when outputting the instruction address to cause the instruction cache to perform an instruction fetch procedure. In accordance with the present invention, a coprocessor is provided for executing a first predetermined instruction also executed by the processor core, the first predetermined instruction causing the coprocessor to issue the predetermined control signal to the instruction cache, and causing the processor core to output to the instruction cache the instruction address data for an instruction to be added to the instruction cache without issuing the predetermined control signal. Further, the instruction cache is responsive to the predetermined control signal from the coprocessor and the instruction address from the processor core to perform the instruction fetch procedure, and, if this results in a cache miss, to cause the retrieval of the instruction from memory for storage in the instruction cache, the processor core being arranged to ignore the retrieved instruction. The above approach allows an instruction to be pre-fetched and stored in the instruction cache without that instruction being returned to the processor core for execution, and without any additional logic needing to be added to the instruction cache to support pre-fetching.

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Cambridge, United Kingdom

Nicholas Andrew Salter