Arm Limited

Nicholas Andrew Plante

Yasuo Ishii

Joseph Michael Pusdesris

William Elton Burky

Alexander Cole Shulyak

Glen Andrew Harris

Abhishek Raja

Muhammad Umar Farooq

Chris Abernathy

Michael Brian Schinzler

Michael David Achenbach

Bipin Prasad Heremagalur Ramaprasad

Jungsoo Kim

Eric Charles Quinnell

Steven Daniel Maclean

Joshua David Knebel

Li Ma

Nicholas Todd Humphries

In register renaming circuitry architectural registers specified in instructions are mapped to physical registers using a mapping table. Operations to be performed with respect to the physical registers are generated in dependence on the instructions and on the mapping table entries. When the mapping table has a mapping of a first instruction destination physical register for a first instruction destination architectural register specified in a first instruction, a second instruction specifying the first instruction destination architectural register as a second instruction source architectural register causes an adapted second operation to be generated corresponding to the second instruction using at least one first instruction source physical register as at least one second instruction source physical register. The adapted second operation incorporates a first operation corresponding to the first instruction.

Register rename stage fusing of instructions

There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

Memcpy micro-operation reduction

There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

Compression of entries in a reorder buffer

A data processing apparatus includes detection circuitry that detects a parent instruction and a child instruction from a stream of instructions. The parent instruction references a destination register that is referenced as a source register by the child instruction. Adjustment circuitry then adjusts the child instruction to produce an adjusted child instruction whose behaviour is logically equivalent to a behaviour of executing the parent instruction followed by the child instruction.

Instruction fusion

A data processing apparatus is provided. Rename circuitry performs a register rename stage of a pipeline by storing, in storage circuitry, mappings between registers. Each of the mappings is associated with an elimination field value. Operation elimination circuitry replaces an operation that indicates an action is to be performed on data from a source register and stored in a destination register, with a new mapping in the storage circuitry that references the destination register and has the elimination field value set. Operation circuitry responds to a subsequent operation that accesses the destination register when the elimination field value is set; by obtaining contents of the source register, performing the action on the contents to obtain a result, and returning the result.

Operation elimination

A predicated-loop-terminating branch instruction controls, based on whether a loop termination condition is satisfied, whether the processing circuitry should process a further iteration of a predicated loop body or process a following instruction. If at least one unnecessary iteration of the predicated loop body is processed following a mispredicted-non-termination branch misprediction when the loop termination condition is mispredicted as unsatisfied for a given iteration when it should have been satisfied, processing of the at least one unnecessary iteration of the predicated loop body is predicated to suppress an effect of the at least one unnecessary iteration. When the mispredicted-non-termination branch misprediction is detected for the given iteration of the predicated-loop-terminating branch instruction, in response to determining that a flush suppressing condition is satisfied, flushing of the at least one unnecessary iteration of the predicated loop body is suppressed as a response to the mispredicted-non-termination branch misprediction.

Responding to branch misprediction for predicated-loop-terminating branch instruction

Growing community of inventors

Austin, TX, United States of America

Nicholas Andrew Plante