Digital Equipment Corporation

Nicholas A Warchol

Chester W Pawlowski

David Gerard Conroy

R Stephen Polzin

Donald W Smelser

Paul S Rotker

Gary P Lidington

Paul M Kinzelman

An apparatus including a system bus coupled to an I/O interface which includes a pointer register and a rejecting circuit which determines whether a write to the pointer register will be accepted or rejected. The I/O interface is further coupled to at least one I/O bus having at least one I/O device connected thereto. The system bus is further coupled to a main memory and to a Central Processing Unit (CPU) which is capable of executing software instructions, providing a command structure corresponding to an access of an I/O device, and writing to the pointer register an address of a location in main memory of the command structure. The CPU further includes a hardware indicator responsive to the rejecting circuit for providing a status signal indicating the status of a write to the pointer register. The CPU executes the software in accordance with the status signal. The apparatus allows the software being executed by the CPU to software pend accesses to devices not directly connected to the system bus. This improves system performance over non-pended system buses and reduces the amount of hardware needed as compared to pended system buses.

System for checking the acceptance of I/O request to an interface using

The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.

Mechanism for screening commands issued over a communications bus for

A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.

Method for control of random test vector generation

A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable connection of a serial control bus to the modules is provided. Accordingly, backplane connectors are provided including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided. A console panel is provided in the computer system comprising LED's visible to the user, each LED corresponding to a particular module. Any LED which remains lit indicates the failure of the corresponding module. Finally, a method and apparatus is provided for maintaining a power system status history. Status indicators corresponding to various environmental conditions in the system are supplied. When any status indicator changes value, the status indicators are stored in a non-volatile memory. In the event of a system shutdown, the nonvolatile memory then retains a status history representing the environmental changes prior to shutdown.

Method and apparatus for displaying module diagnostic results

A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated circuit. The group of test strings is searched to locate a sequence of test strings having a undesirable pattern. The undesirable pattern can be a pattern in which none of the elements associated with the test string changes or a pattern in which a reference element and at least one other element of the test string changes. When a sequence of test strings having the undesirable pattern is located, the group of test strings is processed to correct the undesirable pattern. When all the vector sequences having an undesirable patterns are corrected, the group of test vectors is applied to the input pins of the integrated circuit.

Method for providing minimal size test vector sets

A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable means for connecting a serial control bus modules is provided. Accordingly, backplane connectors are provide including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided. A console panel is provided in the computer system comprising LED's visible to the user, each LED corresponding to a particular module. Any LED which remains lit indicates the failure of the corresponding module. Finally, a method and apparatus is provided for maintaining a power system status history. Status indicators corresponding to various environmental conditions in the system are supplied. When any status indicator changes value, the status indicators are stored in a non-volatile memory. In the event of a system shutdown, the non-volatile memory then retains a status history representing the environmental changes prior to shutdown.

Method for testing a processor module in a computer system

A termination component that is capable of configuring itself to accommodate buses having different electrical characters that connect to it. The termination component includes resistor lines and resistor-diode lines that connect to a power source. These resistor lines and resistor-diode lines when properly powered permit the self-configuration of the termination component.

Self-configuring bus termination component

A cache memory exchange protocol that utilizes an exchange memory access request is provided A cache controller issues the exchange request over a system bus to a main memory in response to a cache miss if the cache location is dirty. Upon receiving the request, the main memory decodes the request and fetches a block of information desired by the transfers a dirty cache block of information over the system bus and stores the dirty block in a temporary register located in the main memory. The block of information desired by the CPU is thereafter transferred by the main memory to the CPU via the system bus. The dirty cache block residing in the temporary register is then stored in the main memory storage elements.

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Boxborough, MA, United States of America

Nicholas A Warchol