Lsi Logic Corporation

Lsi Corporation

Nicholas A Oleksinski

David W Vinke

Ekambaram Balaji

Michael A MInter

Balaji Ganesan

A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Generic methodology to support chip level integration of IP core instance constraints in integrated circuits

A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.

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Northville, MI, United States of America

Nicholas A Oleksinski