Xilinx, Inc.

Nicholas A Mezei

Steven Banks

Raymond Kong

Sankaranarayanan Srinivasan

Pradip Jha

Chun Zhang

Satish B Sivaswamy

Walter A Manaker, Jr

Mehrdad Eslami Dehkordi

Frederic Revenu

Garik Mkrtchyan

Atul Srinivasan

Frank Mueller

Meiwei Wu

David A Ewing

Thomas O Satter

Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.

Partial reconfiguration of integrated circuits using shell representation of platform design

Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.

Method and apparatus for placement and routing of circuit designs

Various approaches for incrementally updating the timing of an implementation of an electronic circuit design are disclosed. In one approach, a subset timing graph is selected from a primary timing graph. Alternative subset timing graphs are generated that are functionally equivalent and structurally different with respect to the selected subset timing graph. For each of the alternative timing graphs, a respective timing metric is determined. The determined timing metrics and a timing metric for the selected subset timing graph are compared. An alternative timing graph is selected in response to the comparison. Structurally different portions of the selected one of the one or more alternative timing graphs are verified with regard to the design constraints. The structurally different portions are stored to the primary timing graph.

Efficient timing graph update for dynamic netlist changes

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Thornton, CO, United States of America

Nicholas A Mezei