Telefonaktiebolaget Lm Ericsson (Publ)

Nianxiong Tan

Svante Signell

Bengt Erik Jonsson

Helge Stenstrom

Hans Mikael Gustavsson

In a digital BiCMOS process the storage capability of MOS transistors and the large transconductance of bipolar transistors can be utilized in such a way, that the speed is primarily determined by the capacitance seen by the MOS transistor (4) and the transconductance of the bipolar transistor (5). The advantages over the prior SI technique in CMOS are higher speed, smaller errors and higher accuracy. The advantages over other techniques in BiCMOS are smaller errors and higher accuracy. The unique feature of the invented technique is the combination of high input impedance of the MOS devices and high transconductance of the bipolar devices, where both devices are only available in BiCMOS process and not in the CMOS process.

Method and device for processing sampled analogue signals in digital

D/A-conversion of a Gray coded digital input signal is performed according to an inventive recursive Gray code-to-analog conversion algorithm. According to the recursive algorithm, the Gray code bits of the digital input are successively applied in the recursions of the algorithm, one Gray code bit for each recursion, and the analog output signal is generated by recursively updating an intermediate signal. In each recursion, the intermediate signal is selectively inverted in dependence on the particular Gray code bit that is applied in the recursion. The selective inversion of the intermediate signal is an inherent property of the Gray code-to-analog algorithm, and it is a key factor to reduce the accumulation of errors in a D/A-conversion. In a D/A-converter architecture based on the algorithm, the accumulation of offset errors will be low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations, further improving the performance of the D/A-converter.

Digital-to-analog conversion of LSB-first type using selective inversion

Pipeline A/D-conversion of an analog input signal is performed according to a new and inventive algorithm which generates a Gray coded digital output signal. A pipeline A/D-converter comprises a number of cascaded stages through which the analog input signal is propagated. Each stage generally generates an output bit of the digital output signal, and furthermore processes the pipeline signal. According to the inventive Gray coding algorithm, the output bit generated in a stage determines whether or not the pipeline signal of that stage is inverted. In a pipeline A/D-converter based on the Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the inventive pipeline A/D-converter. In another embodiment of the invention, the Gray coding algorithm is modified to form a second algorithm which makes low device count implementations possible.

Pipeline analog-to-digital conversion that reduces the accumulation

Cyclic A/D-conversion of an analog input signal is performed according to a new and inventive recursive algorithm which generates a Gray coded digital output signal. In cyclic A/D-conversion, the output bits are generated cyclically, one by one. According to the inventive Gray coding algorithm, the analog input signal is cyclically subjected to a sample and hold operation, selectively, depending on the previously generated output bit, to a signal inversion, to an amplification by two, and to an addition of a predetermined reference signal. In a cyclic A/D-converter architecture based on the recursive Gray coding algorithm according to the invention, the accumulation of offset errors will generally be very low. Furthermore, the fact that the signal inversion is digitally controlled enables high precision implementations which further improve the performance of the cyclic A/D-converter according to the invention.

Cyclic analog-to-digital converter that reduces the accumulation of

To convert an analog current to a digital signal using a high-speed pipelined analog-to-digigal (A/D) converter, the A/D converter may comprise a current sample- and hold (S/H) circuit at the input and several identical pipelined stages, where each stage contains a current S/H circuit, a current interstage low-resolution A/D converter and current references. To improve the speed of pipelined current-mode A/D converters the capacitive load seen by the output of every stage will be reduced. By adjusting the reference currents the power consumption will also be reduced. It is possible to achieve about 100 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs. To increase the operation speed and to provide means to reduce the power consumption the pipelined current-mode A/D converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.

Current-mode pipelined ADC with time-interleaved sampling and mixed

Most temperature related reference generations are in the voltage domain, which means that reference voltages rather than reference currents are generated. In some applications such as driving laser diodes, currents are needed rather than voltages. In the present invention, as an alternative, the references are designed in the current domain, wherein the operation philosopy can be said to be inverse to the operation philosopy of the prior art. The temperature dependence of the currents are known and the currents (1, 2) will be processed by linear and/or non linear operation to generate currents (3) with predetermined temperature coefficients. The advantages of the invention can be outlined as more straight forward, scaling and summation (subtraction) are much easier and simpler in the current domain than in the voltage domain.

Method and device for temperature dependent current generation

High-speed and high accuracy digital-to-analog (D/A) converters find many applications in signal processing. For wideband telecommunication systems, there is a strong demand on high-performance D/A converters. With the design of the present invention it is enabled to prevent distortions and intermodulations for high-speed and high-accuracy digital-to-analog (D/A) converters for telecommunication applications, where the requirements on distortion and intermodulation can be very stringent. By combining segmentation for MSBs and binary weighting for LSBs a high-performance digital-to-analog conversion architecture can be achieved, where a delay for the binary weighted LSBs is used to equalize a delay introduced by segmentation and where all bit switches (14) are clocked with a tree-like-clock distribution network (11). New floor plans for CMOS, BiCMOS and bipolar implementation are thus invented and circuits for CMOS bit switches and current sources are also disclosed.

Method and device to provide a high-performance digital-to-analog

A voltage-to-current converter for converting an input voltage signal into an output current signal, while providing a filtering function. The input voltage signal is converted to an intermediate current signal by an input resistance and an equivalent resistance provided by, for example, an inverting amplifier and a transistor. A current mirror having a dominant pole converts the intermediate current signal to the output voltage signal, and provides low pass filtering. The converter avoids the use of linear capacitors, and can be easily implemented in a CMOS device.

Voltage-to-current converter

A noise-limiting, switched current delta-sigma modulator for use in, for example, an oversampling analog-to-digital converter. The modulator includes a first integrator having a relatively large bias current and one or more second integrators having relatively small bias currents. The modulator according to the present invention reduces power consumption and chip area.

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Nianxiong Tan