Atmel Corporation

Silicon Storage Technology, Inc.

Nianglamching Hangzo

Glen Arnold Rosendale

Saroj Pathak

James E Payne

Hung Quoc Nguyen

Sang Thanh Nguyen

Jagdish Pathak

A memory device includes a sense circuit comprising a sense amplifier, a reference sense circuit and a comparator. The sense amplifier detects a signal on a bit line associated with a column of memory cells in a memory array. The reference sense circuit detects a signal on a reference bit line associated with a column of reference cells in the memory array. The comparator compares the outputs of the sense amplifier and the reference sense circuit and provides a signal indicative of the contents of the read memory cell. In response to a transition of an address, the bit line and the reference bit line are precharged prior to reading of the memory cell. The reference sense circuit includes a selectable load that is disabled during the initial time after the address transition so that the bit line and the reference bit line rises substantially identically and then enabled to allow the reference bit line to settle to a steady state.

Bitline precharge matching

A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.

Circuit for transferring high voltage video signal without signal loss

A video chip includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register. There is a circuit for the column lines and for the row lines. A bit pattern is driven onto the column or the row lines and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.

Method and apparatus for testing a video display chip

A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.

Sense amplifier with zero power idle mode

A serial configuration memory device comprises an architecture wherein the reading out of data and the outputting of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.

Zero power high speed configuration memory

A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

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San Jose, CA, United States of America

Nianglamching Hangzo