Digital Equipment Corporation

Niamh Darcy

Simoni Ben-Michael

Michael Ben-Nun

Steven Ho

Yifat Ben-Shahar

Winthrop J Wu

Eitan Medina

In an asynchronous transfer mode (ATM) endnode a method is provided by which ATM cells can experience a small delay from the ATM layer to the PHY layer to transmission on the ATM network. Such an arrangement includes providing the endnode with an ATM layer, the ATM layer having a first-in-first-out (FIFO) queue for transmitting transmit ATM traffic, providing the endnode with a PHY layer, the PHY layer having a FIFO queue for receiving the transmit ATM traffic, providing an interface between the FIFO queue of the ATM layer and the FIFO queue of the PHY layer for the flow of the transmit ATM traffic, providing a signal in the ATM endnode, providing a state machine in the ATM endnode, the state machine monitoring the signal in the ATM endnode, stalling the transfer of the transmit ATM traffic from the FIFO of the ATM layer to the FIFO of the PHY layer over the interface when the signal and the state machine indicate that the FIFO of the PHY layer is full, and transmitting the transmit ATM traffic from the FIFO of the ATM layer to the FIFO of the PHY over the interface. By causing the ATM layer to generate/transfer a continuous stream of cells to the PHY layer, the method can provide cell time indications to allow the ATM layer to synchronize itself to the network.

Method for controlled-latency transfer of transmitt ATM traffic and

A method providing automating detection of configuration between an adapter device and a DRAM device. Such a method a determines, in the adapter memory, the DRAM configuration, making it easier to change DRAM configuration in an existing board without the need to modify configuration pins in the existing board. A method for determining a configuration type in an Asynchronous Transfer Mode (ATM) communications network comprising the steps of providing an ATM adapter, the ATM adapter having an ATM adapter memory, providing a DRAM device, the DRAM device having a DRAM configuration, providing a link to connect the ATM adapter and the DRAM device, assuming, in the ATM adapter memory, a first DRAM configuration, verifying the step of assuming, and repeating the steps of assuming and verifying until the first DRAM configuration is determined.

Method for detection of configuration types and addressing modes of a

A clock mechanism in modules connected to a bus over which asynchronous operations are performed wherein clock pulses are generated that can clock the transmission or capture of data and the transitioning of acknowledge or synchronization lines. Each clock mechanism generates its clock pulses based on the receipt of signals associated with synchronization or acknowledge bus lines. The clock mechanism includes a multiplexer which provides to a resettable latch a signal associated with the condition of the selected line. The resettable latch, in conjunction with a delay element produces the clock pulses.

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Acton, MA, United States of America

Niamh Darcy