Analog Devices,inc.

Niall Daniel O'Connell

Seamus Ryan

Wei Che

Tianjiang Li

Weijun Xu

Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Video processor timing generation

A method for deriving a synchronisation signal () from a video signal comprises tracking the blanking level () of the video signal with first and second slice level signals () and tracking the sync tip level () of the horizontal sync signal () of the video signal with third and fourth slice level signals () for determining the blanking level () and the sync tip level (). A value for an intermediate slice level signal () is computed from the first, second, third and fourth slice level signals () so that the value of the intermediate slice level signal () lies approximately halfway between the blanking level () and the sync tip level (). The video signal is compared with the intermediate slice level signal (), and the synchronisation signal () is prepared from a logic signal by transitioning the logic signal from one of the logic high and logic low levels to the other of the logic high and logic low levels, each time the video signal transitions across the intermediate slice level signal ().

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Limerick, Ireland

Niall Daniel O'Connell