Analog Devices Global Unlimited Company

Analog Devices International Unlimited Company

Analog Devices Global

Niall D O'Connell

Isaac Molina Hernandez

John Cullinane

Anand Venkitasubramani

Pablo Ventura

Sean M Mullins

Bhavana Muralikrishna

Shreeja Sugathan

David Rowe

Amogh D Thaly

Alan M Barry

David O'Neill

Lucas Valentin Garcia

There is disclosed in one example a video processor, including: an input buffer to receive an input image; a slicer circuit to divide the input image into a plurality of N vertical slices; N parallel input buffers for de-rasterization; N parallel image scalers, wherein each scaler is hardware configured to scale in a raster form, one of the N vertical slices according to an image scaling algorithm; N parallel output buffers for rerasteriztion; and an output multiplexer to combine the scaled vertical slices into a combined scaled output image.

Image scaling

Disclosed herein are systems and methods for performing SAG effect compensation on a video signal received over an AC-coupled video link. In one aspect, a method for performing SAF effect compensation includes applying a filter to the received video signal to generate a corrected video signal, where a transfer function of the filter is dependent on a transmission parameter that is based on a plurality of parameters of the AC-coupled link. The method further includes extracting predefined content from the corrected video signal, and adjusting the transmission parameter based on a comparison of the extracted predefined content with certain expected content, so that adjusted transmission parameter can be used for one or more subsequent applications of the filter, thereby realizing an adaptive filter.

Methods and devices for compensating sag effect

Disclosed herein are systems and methods for performing DC offset correction of a video signal received over an AC-coupled video link. In one aspect, a transmitter is configured to compute, and provide to a receiver, metadata indicative of a statistical characteristic (e.g., an average or a sum of values) for a group of active pixels of a video signal acquired by a camera. The receiver is configured to compute an analogous statistical characteristic on the video signal received over an AC-coupled video link, and to perform DC offset correction by modifying one or more values of the received video signal based on a comparison of the statistical characteristic computed by the receiver and the one computed by the transmitter and indicated by the received metadata.

Using metadata for DC offset correction for an AC-coupled video link

Disclosed herein are systems and methods for communicating video signals and control data over a HD, wired, AC-coupled video and control link. In one aspect, an example system includes a scheduler that is configured to allocate time slots for exchange of data between a transmitter and a receiver over such a link. The scheduler is configured to, for each of at least one or more video lines of a video frame of a video signal acquired by a camera, allocate a plurality of time slots for transmitting a plurality of video components of said video line from the transmitter to the receiver, allocate one or more time slots for transmitting transmitter control data from the transmitter to the receiver, and allocate one or more time slots for transmitting receiver control data from the receiver to the transmitter.

High definition analog video and control link for automotive applications

This disclosure relates generally to communicating video content and other data over networks. An example apparatus includes a transmitter for communicating data via a serial link with a receiver. The transmitter includes an input, an output interface to the serial link, and translation circuitry. The input includes multiple input data lanes and a clock lane, and the input is configured to concurrently receive data on the multiple input data lanes aligned with a clock signal received on the clock lane according to a multi-lane communication protocol. The output interface is a clock-less interface and includes a number of output data lanes less than a number of the multiple input data lanes. The translation circuitry translates the data received according to the multi-lane communication protocol to a serial link communication protocol for transmission on the serial link.

High speed serial link for video interfaces

Growing community of inventors

Clarina, Ireland

Niall D O'Connell