Intel Corporation

Niall D McDonnell

Stephen R Van Doren

Andrew Cunningham

Joseph Nuzman

William G Burroughs

Bruce Richardson

David Sonnier

Gage Eads

Lokpraveen B Mosur

Tomasz Kantecki

Robert Valentine

Gilbert A Neiger

Mark Jay Charney

Jesus Corbal

Rajesh M Sankaran

Tsung-Yuan Charles Tai

Ren Wang

Edward Thomas Grochowski

Andrew J Herdrich

Eriko Nurvitadhi

Debra Bernstein

Koichi Yamada

Thomas D Fletcher

Deborah T Marr

Stephen T Palermo

Paul Caprioli

Dennis Ryan Bradford

Narayan Ranganathan

Kent D Glossop

Jonathan D Pearce

Hugh Wilkinson

Richard J Greco

Jeffrey J Cook

Ganesh Venkatesh

Asit K Mishra

Namakkal N Venkatesan

Dwight P Manley

Tracy Garrett Drysdale

David B Sheffield

Jonas Svennebring

Nicholas P Carter

Jonathan Kenny

Michael A O'Hanlon

Jr-Shian Tsai

Edwin Verplanke

Andrey Chilikin

Samantika S Sury

Yipeng Wang

Patrick Fleming

Shrikant M Shah

James T Clee

Narender R Vangati

Jerry Pirog

Joseph R Hasting

Abhishek Khade

Te Khac Ma

Abhirupa Layek

Stephen Miller

Sarita Maini

Bradley Chaddick

An Yan

Jamison D Whitesell

Christopher J Hughes

Yen-Cheng Liu

Eliezer Tamir

David A Koufaty

Chris MacNamara

Rahul R Shah

Bradley A Burres

Pierre Laurent

Doddaballapur N Jayasimha

Stephen J Robinson

Christopher MacNamara

John Wishneusky

Mrittika Ganguli

Brian A Keating

Bjorn Topel

John Mangan

Carl-Oscar Montelius

Anil Vasudevan

John Joseph Browne

Ben-Zion Friedman

Ilango S Ganga

Patrick G Kutch

Rahul C Shah

Durgesh Srivastava

Neelam Chandwani

Chetan Hiremath

Mark D Gray

Daniel G Borkowski

Rakesh Dodeja

Brendan Ryan

Alexander J Leckey

Sean Harte

Naveen Lakkakula

Ciara Loftus

Harry Van Haaren

Yean Kee Yong

Venkidesh Krishna Iyer

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Systems, methods, and apparatuses for heterogeneous computing

Examples described herein include a system comprising: a processing unit package comprising: at least one core and at least one offload processing device communicatively coupled inline between the at least one core and a network interface controller, the at least one offload processing device configurable to perform packet processing. In some examples, the at least one offload processing device is to allow mapping of packet processing pipeline stages of networking applications among software running on the at least one core and the at least one offload processing device to permit flexible entry, exit, and re-entry points among the at least one core and the at least one offload processing device.

Network and edge acceleration tile (NEXT) architecture

Aspects of data re-direction are described, which can include software-defined networking (SDN) data re-direction operations. Some aspects include data re-direction operations performed by one or more virtualized network functions. In some aspects, a network router decodes an indication of a handover of a user equipment (UE) from a first end point (EP) to a second EP, based on the indication, the router can update a relocation table including the UE identifier, an identifier of the first EP, and an identifier of the second EP. The router can receive a data packet for the UE, configured for transmission to the first EP, and modify the data packet, based on the relocation table, for rerouting to the second EP. In some aspects, the router can decode handover prediction information, including an indication of a predicted future geographic location of the UE, and update the relocation table based on the handover prediction information.

Software-defined networking data re-direction

Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.

Spatial and temporal merging of remote atomic operations

Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

Virtual switch scaling for networking applications

Techniques and apparatus for processor queue management are described. In one embodiment, for example, an apparatus to provide queue congestion management assistance may include at least one memory and logic for a queue manager, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to determine queue information for at least one queue element (QE) queue storing at least one QE, compare the queue information to at least one queue threshold value, and generate a queue notification responsive to the queue information being outside of the queue threshold value. Other embodiments are described and claimed.

Techniques for processor queue management

A computing apparatus, including: a processor; a pointer to a counter memory location; and a lazy increment counter engine to: receive a stimulus to update the counter; and lazy increment the counter including issuing a weakly-ordered increment directive to the pointer.

Lazy increment for high frequency counters

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache ('LLC'), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

Multi-core communication acceleration using hardware queue device

Growing community of inventors

Limerick, Ireland

Niall D McDonnell