Stmicroelectronics (shenzhen) R&d Co. Ltd.

Shenzhen Sts Microelectronics Co., Ltd.

Ni Zeng

Da Song Lin

Gang Zha

Yiwei Zhang

Xianfeng Xiong

Dasong Lin

Gangqiang Zhang

A low dropout amplifier may include an error amplifier having first and second inputs coupled to a reference signal and a feedback signal, respectively. The error amplifier may be configured to generate first and second error signals at first and second outputs, respectively, with the first and second error signals based upon a difference between the reference signal and the feedback signal. A sink stage may be coupled to the first output and configured to generate a sink current based upon the first error signal. A source stage may be coupled to the second output and configured to generate a source current based upon the second error signal. An output node may be coupled to receive the sink and source currents.

Two-stage error amplifier with nested-compensation for LDO with sink and source ability

A current limiting circuit includes a current sensing module that is configured to sense an output current of a power transistor and to generate a corresponding sensing current which is proportional to the output current. A first current limiting module coupled to the current sensing module is configured to generate a first limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a first current level. A second current limiting module coupled to the current sensing module is configured to generate a second limiting current based on the sensing current when a variation of the output current of the power transistor exceeds a second current level. A converting module coupled to the first and second current limiting modules and the power transistor controls a gate voltage of the power transistor based at least on the first and second limiting currents.

Current limiting circuit

A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

Driver circuit with gate clamp supporting stress testing

A generator circuit is coupled to apply a control signal the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

Driver circuit for driving power transistors

An embodiment of the invention relates to a power converter formed with an error amplifier and a related method. In an embodiment, a first switch is coupled in series with an error amplifier compensation capacitor. Upon detection of a current level greater than a threshold level, the compensation capacitor is decoupled from the error amplifier by opening the first switch. In an embodiment, a second switch is coupled in parallel with the compensation capacitor, and the current-sensing circuit enables conductivity of the second switch to discharge the compensation capacitor upon detection of the current level greater than the threshold level. The second switch is opened upon detection of the current level less than the threshold level. In an embodiment, the current-sensing circuit controls an output current of the power converter at a current-limit level upon detection of the internal current level greater than the threshold level.

Regulator over-voltage protection circuit with reduced standby current

An LIN transmitter includes a current mirror coupled to a transmit output node and a control circuit coupled to a transmit input node for controlling the current mirror with various load current control signals.

Half open-loop-controlled LIN transmitter

Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector.

Temperature-independent undervoltage detector and related method

A LIN receiver circuit includes filtering circuitry receiving an input signal and producing a filtered signal, a first comparator comparing the filtered signal to a threshold voltage, and a driver block producing the receiver output signal. The receiver circuit further includes an input comparator, signal-adjusting circuitry, and deglitching circuitry. The input comparator detects a low voltage on the input signal, and the signal-adjusting circuitry drives the filtered signal to a particular value to shorten the length of a glitch at the output of the first comparator. Meanwhile, the deglitching circuitry detects and removes the glitch to produce a deglitcher output signal. The deglitcher output signal is received by the driver block, which outputs the receiver output signal, wherein the receiver output signal contains no glitches, and is delayed by no more than 7.5 &#x3bc;s, thus providing immunity to ISO pulses.

LIN receiver providing immunity against ISO pulses

A precise over-voltage comparator exhibits zero-waiting-current characteristics during normal working conditions. An NMOS transistor is used in conjunction with other circuit elements to regulate the over-voltage comparator. For normal power supply voltages, the comparator stays in standby status and does not consume quiescent current.

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Shenzhen, China

Ni Zeng