Intel Corporation

Ni Jie

Brian M Leitner

Dominic J Gasbarro

Tom E Burton

Dean Stuart Susnow

Richard D Reohr, Jr

Brian M Collins

David L Chalupsky

Dick Reohr

Packet sequence numbers of request packets and response packets of transactions transferring data to or from a network interface are tracked. For every request packet transmitted by the network interface, the packet sequence number of the packet is written to a location in a circular send queue pointed to by a write pointer and a valid bit at the location is set. The write pointer is incremented if the packet is a read request packet. Alternatively, a read indicator at the location in the circular send queue pointed to by the write pointer is cleared if the packet is not a read request packet. For every response packet received by the network interface, the packet sequence number of the response packet is checked against the packet sequence number stored at the location in the circular send queue pointed to by the read pointer of the circular send queue.

Memory utilization in a network interface

A test bus architecture for testing an integrated circuit having a plurality of agents includes providing both a test block select signal and test function select signal to a plurality of select decoders respectively disposed in each of the plurality of agents. The test block select signal has a number of states at least equal to the number of agents and the test function select signal at least equal to a maximum number of internal signal groups of any one of the agents, each select decoder having at least one internal signal group which is outputted from circuitry to be tested within the agent of the select decoder. An output from each of the select decoders is fed to a test bus output such that a selected internal signal group is outputted to the test bus output upon the agent of the selected signal group being selected by the state of the test block select signal and the selected signal group being selected by the state of the test function select signal by the select decoder.

Test bus architecture

A circuit to control a network interface includes a first interface circuit and a second interface circuit. The first interface circuit is capable of negotiating one protocol to use from a plurality of known interface protocols. The first interface circuit controls the network interface when the negotiated interface protocol is supported by the first interface circuit. Otherwise, if the second interface circuit supports the negotiated protocol, the first interface circuit releases control of the network interface to the second interface circuit. The first interface circuit takes control of the network interface from the second interface circuit when the second interface circuit signals the first interface circuit that reliable communication with the network has been lost.

Method and apparatus for supporting multiple protocols on a network

Growing community of inventors

Portland, OR, United States of America

Ni Jie