Emc Corporation

The Charles Stark Draper Laboratory, Inc.

Nhut Tran

William F Baxter

Michael Sgrosso

James Marriott Guyer

J Ryan Prince

Christopher S MacLellan

Brian Nugent

Elliot Greenwald

Martin Klingensmith

An embodiment is directed to a hardware circuit for encrypting and/or decrypting data transmitted between a processor and a memory. The circuit is situated between the processor and memory. The circuit includes a first interface communicatively coupled to the processor via a set of buses. The circuit also includes a second interface communicatively coupled to the memory. The circuit further includes hardware logic capable of executing an encryption operation on data transmitted between the processor and memory, without adding latency to data transmission speed between the processor and the memory. The hardware logic is configured to encrypt data received at the first interface from the processor, and transmit the encrypted data to the memory via the second interface. The hardware logic is also configured to decrypt data received at the second interface from the memory, and transmit the decrypted data to the processor via the first interface.

Latency free data encryption and decryption between processor and memory

An embodiment is directed to a hardware circuit for performing operations on data transmitted between a processor and memory. The hardware circuit includes a first interface communicatively coupled to the processor. The first interface configured to emulate a first protocol of the memory. The hardware circuit further includes a second interface communicatively coupled to the memory. The second interface configured to emulates a second protocol of the processor. The hardware circuit also includes hardware logic configured with a bi-directional path, such that each of the first and second interfaces is associated with a different direction of the bi-directional path. The bi-directional path is configured to execute an operation on data received at both the first interface and the second interface.

Fast XOR interface with processor and memory

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Data storage system having acceleration path for congested packet switching network

A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.

Data storage system having operation code in address portion for atomic operations

Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request

Data storage system having separate atomic operation/non-atomic operation paths

Growing community of inventors

Natick, MA, United States of America

Nhut Tran