Exelis Inc.

Itt Manufacturing Enterprises, Inc.

Corrent Corporation

Nhu-Ha Yup

Kevin J Osugi

Lee Noehring

Richard J Takahashi

Satish N Anand

Bryan Doi

Darren L Parker

Michael Dean Collins

Lee P Noehring

Michael D Collins

Darren Parker

Architecture for embedding a cryptographic engine in a processor is disclosed. An ASIC processor is embedded with a programmable processing core, such as an FPGA, with the key register and I/O registers remaining in fixed logic.

Configurable ASIC-embedded cryptographic processing engine

An authenticated encryption method includes receiving, by an Advanced Encryption Standard (AES) engine, a cipher key and computing a hash key using the received cipher key. The computed hash key is stored in a storage memory. The AES engine then receives a packet of data and encrypts the packet of data using the received cipher key. The hash key from the storage memory is sent to a GHASH engine which is used to authenticate the packet of data. Encrypting the packet of data is performed after the hash key is stored in the storage memory. Input flow of the packet of data is enabled after the hash key is stored in the storage memory.

Precalculated encryption key

A combination firmware and hardware cryptographic core architecture is provided for encrypting, decrypting and authenticating data. The core provides flexibility to change and add new cryptographic protocols, while providing increased performance by loading new firmware into a microcontroller that programs behavior of various components in the core. The core combines a microcontroller programmable by firmware, and flexible aligner, insertion and removal controllers programmed by the microcontroller that process, manage and manipulate an incoming data stream as it moves through the core. The firmware may be reprogrammed upon an enhancement or change to a protocol while still realizing performance benefits of the hardware. Reprogramming the microcontroller allows it to change the way the aligner, insertion and removal controllers manipulate the data stream as it enters various components. Such systems provide redesign time savings compared to hardware cryptographic core architectures, and improved speed and throughput compared to software cryptographic core architectures.

Method and system for cryptographic processing core

A firmware cipher component is provided which can be configured and programmed to efficiently implement a broad range of cryptographic ciphers while accelerating their processing. This firmware cipher component allows an ASIC to support multiple cipher algorithms while accelerating the operations beyond speeds conventionally achieved by software or firmware only solutions. This system combines cryptographic specific custom instructions with hardware based data manipulation accelerators. The cryptographic specific custom instructions and hardware accelerators may support both block and stream ciphers. Thus, the system may be reconfigured, allowing the cipher algorithm to change without halting the system. Further, embedding the Firmware Programmable Cipher within an ASIC may allow future capabilities to be supported in secure applications.

Method and system for embedded high performance reconfigurable firmware cipher

A circuit includes a single circuit portion for implementing the Advanced Encryption Standard (AES) block cipher algorithm in a system having a plurality of channels. The circuit portion includes a circuit for individually generating, on the fly, the round keys used during each round of the AES block cipher algorithm. The circuit portion also includes shared logic circuits that implement the transformations used to encrypt and decrypt data blocks according to the AES block cipher. The single circuit portion encrypts or decrypts data blocks from each of the plurality of system channels in turn, in round-robin fashion. The circuit portion also includes a circuit for determining S-box values for the AES block cipher algorithm. The circuit additionally implements an efficient method for generating round keys on the fly for the AES block cipher decryption process.

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Phoenix, AZ, United States of America

Nhu-Ha Yup