Intel Corporation

Qualcomm Incorporated

Juniper Networks, Inc.

Microsoft Technology Licensing, LLC

Advanced Micro Devices Corporation

Other

Globalfoundries Inc.

Nhon Toai Quach

Edward Thomas Grochowski

John H Crawford

Chakravarthy Kosaraju

Sunny C Huang

Greg Mathews

Dean A Mulla

Jeen Miin

Moinul H Khan

William Rash

Ramesh Padmanabhan

Jean Marc Frailong

John Wai Fu

Koichi Yamada

Gary N Hammond

Yanru Li

Rahul Gulati

Asit K Mallick

Martin Renschler

Suresh K Marisetty

Mani Ayyar

Maurice Franklin Ribble

Bernard Lint

Amy L O'Donnell

Len J Schultz

Venkatesh Nagapudi

Ning Bi

Robert Hardacker

Hang T Nguyen

Sean Lie

Sorin Iacobovici

Gregory Scott Mathews

Susan Elizabeth Carrie

Mainak Biswas

Michael Paul Corwin

Alberto J Munoz

Jeffrey Andrews

Ramesh Chandrasekhar

Haw-Jing Lo

Rashmi Kulkarni

John Victor Sell

Ranganathan Sudhakar

Michael Drop

Mehrad Tavakoli

Assaf Menachem

Tracy Sharpe

James O Hays

Jeffrey Shabel

Kin-Yip Liu

Virat Deepak

Stuart E Sailer

Pranjal Bhuyan

Ricky Wai Kit Yuen

Valentin Anders

Stephen Z Au

Andres Rabago

Jim Hays

John W C Fu

Oscar Cabral Arias

Venkata Narayana Ramesh Pinnamaraju Durga

Kevin Po

Thomas Zou

Mattheus Heddes

SeongWoo Kim

Huang Kuang Hu

Todd Lemoine

Maurice Ribble

John Sell

Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

Systems and methods for implementing error correcting code in a memory

Certain aspects of the present disclosure provide methods and apparatus for operating a wearable display device. Certain aspects of the present disclosure provide a method for operating a wearable display device. The method includes determining a position of the wearable display device based on a motion sensor. The method includes rendering, by a graphics processing unit, an image based on the determined position. The method includes determining a first updated position of the wearable display device based on the motion sensor. The method includes warping, by a warp engine, a first portion of the rendered image based on the first updated position. The method includes displaying the warped first portion of the rendered image on a display of the wearable display device.

Display synchronized image warping

Systems and methods are disclosed for implementing error correction control regions (ECC) in a memory device without the need to ECC protect the entire memory device. An exemplary method comprises defining one or more ECC regions in a memory device, the memory device coupled to a system on a chip (SoC). An ECC block is provided on the SoC, the ECC block in communication with the one or more ECC regions in the memory device. A determination is made with the ECC block whether to store data in a first of the one or more ECC regions. Responsive to the determination ECC bits are generating for, and interleaved with, the received data and interleaved ECC bits and data are caused to be written to the first ECC region. Otherwise, received data is sent to a non-ECC region of the memory device.

Systems and methods for implementing error correcting code regions in a memory

Systems, methods, and computer programs are disclosed for reducing motion-to-photon latency and memory bandwidth in a virtual reality display system. An exemplary method involves receiving sensor data from one or more sensors tracking translational and rotational motion of a user for a virtual reality application. An updated position of the user is computed based on the received sensor data. The speed and acceleration of the user movement may be computed based on the sensor data. The updated position, the speed, and the acceleration may be provided to a warp engine configured to update a rendered image before sending to a virtual reality display based on one or more of the updated position, the speed, and the acceleration.

Systems and methods for reducing motion-to-photon latency and memory bandwidth in a virtual reality system

Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Systems and methods for reducing volatile memory standby power in a portable computing device

Systems and methods for applying a fine-grained QoS logic are provided. The system may include a memory controller, the memory controller configured to receive memory access requests from a plurality of masters via a bus fabric. The memory controller determines the priority class of each of the plurality of masters, and further determines the amount of memory data bus bandwidth consumed by each master on the memory data bus. Based on the priority class assigned to each of the masters and the amount of memory data bus bandwidth consumed by each master, the memory controller applies a fine-grained QoS logic to compute a schedule for the memory requests. Based on this schedule, the memory controller converts the memory requests to memory commands, sends the memory commands to a memory device via a memory command bus, and receives a response from the memory device via a memory data bus.

Fine-grained bandwidth provisioning in a memory controller

One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA&#xae; bus. The interconnect chip may communicate with the IO device via the AMBA&#xae; bus in an AMBA&#xae; compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA&#xae; bus, receiving a response from the IO device over the AMBA&#xae; bus, and sending over the AMBA&#xae; bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules.

Support for IOAPIC interrupts in AMBA-based devices

A network device includes an interface (), a TCP/IP protocol fast processing path (), and a TCP/IP protocol slow processing path (). The interface () receives a packet and parses the packets to determine a characteristic of the packet. The TCP/IP protocol fast processing path () processes the packet if the characteristic of the packet includes a first characteristic. The TCP/IP protocol slow processing path () processes the packet if the characteristic of the packet includes a second characteristic.

Systems and methods for accelerating TCP/IP data stream processing

A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operate in this mode. Floating-point store and integer-transfer unary instructions may be converted to new instructions. Each new instruction has two source operands, each corresponding to a different thread is specified by a same logical register number as a single source operand of the original unary instruction. All other instructions are replicated, wherein the original instruction and its twin are assigned to different threads. Simultaneous multi-threaded (SMT) floating-point logic may only be able to provide lockstep execution when it communicates using the new instruction with instantiated integer independent clusters. The new instruction cannot begin until both source operands are ready, which are subsequently compared to determine any mismatches or errors.

Reliable execution using compare and transfer instruction on an SMT machine

Systems and methods for error handling are disclosed. The systems and methods may be utilized for single or multiple processor computer systems to handle errors in a coordinated manner between hardware and any firmware or software layers. A computer system includes a non volatile memory and at least one processor. A firmware error handling routine is stored on the non volatile memory. The firmware error handling routine is for handling errors. Each of the at least one processors detects errors. Each processor executes the firmware error handling routine on detecting an error. The executed firmware error handling routine handles the error. The executed firmware error handling routine also logs error information to a log. The systems and methods provide for coordinated error handling that enhance error recovery, provide error containment and maintain system availability.

System abstraction layer, processor abstraction layer, and operating system error handling

A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the queue. A first point in time is determined when said first reason no longer prevents exit of the entry from the queue. A second reason which prevents exit of the entry from the queue is detected, wherein the second reason came into existence prior to said first point in time. A second count corresponding to the second reason is incremented, wherein incrementing the second count begins at the first point in time.

Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement

A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

Processor including efficient signature generation for logic error protection

The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

Apparatus and method for protecting critical resources against soft errors in high performance microprocessor

Growing community of inventors

Santa Clara, CA, United States of America

Nhon Toai Quach