Rambus Inc.

Hewlett-packard Company

Nhat M Nguyen

Yohan Usthavia Frans

Masum Hossain

Brian S Leibowitz

Hae-Chang Lee

Simon Li

Yikui Jen Dong

Arash Zargaran-Yazd

Kevin S Donnelly

Charles Walter Boecker

Kenneth Colin Dyer

Wendemagegnehu Beyene

Shankar Tangirala

Todd W Bystrom

Yueyong Wang

Dennis Kim

Mark A Horowitz

Donald C Stark

Bruno Werner Garlepp

Benedict C Lau

Thomas H Lee

Mark G Johnson

Pak Shing Chau

Jun Y Kim

Leung Yu

Chanh Vi Tran

Yiu-Fai Chan

Barry William Daly

Jason C Wei

Michael Green

Kun-Yung Chang

Kevin J Negus

A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Interface with variable data rate

A receiver includes a variable resolution analog-to-digital converter (ADC) and variable resolution processing logic/circuitry. The processing logic may use feed-forward equalization (FFE) techniques to process the outputs from the ADC. When receiving data from a channel having low attenuation, distortion, and/or noise, the ADC and processing logic may be configured to sample and process the received signal using fewer bits, and therefore less logic, than when configured to receiving data from a channel having a higher attenuation, distortion, and/or noise. Thus, the number of (valid) bits output by the ADC, and subsequently processed (e.g., for FFE equalization) can be reduced when a receiver of this type is coupled to a low loss channel. These reductions can reduce power consumption when compared to operating the receiver using the full (i.e., maximum) number of bits the ADC and processing logic is capable of processing.

Variable resolution digital equalization

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

PAM-4 DFE architectures with symbol-transition dependent DFE tap values

A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitryresolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

Methods and circuits for decision-feedback equalization with early high-order-symbol detection

A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitryresolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.

Symbol-rate phase detector for multi-PAM receiver

A PAM-4 DFE receives an input signal distorted by inter-symbol interference (IS I) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitryresolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of IS I offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the IS I offset for the immediate symbol.

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San Jose, CA, United States of America

Nhat M Nguyen