Freescale Semiconductor,inc.

Motorola Corporation

Nhat Dinh Vo

James W Miller

Burton Jesse Carpenter

Tu-Anh N Tran

Sheila F Chopin

Alan H Woosley

Peng Su

Kendall Dewayne Phillips

Dae Y Hong

A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.

Stress relief of a semiconductor device

A pad () is electrically connected to a first I/O cell () while also physically overlying active circuitry of a second I/O cell (). Note that although the pad () overlies the second I/O cell (), the pad () is not electrically connected to the I/O cell (). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g.-) may have a finer pitch than the corresponding pads (-and-). In addition, the size of the pads may be increased (e.g. padmay be bigger than pad) while the width 'c' of the I/O cells (-) does not have to be increased. Such a pattern (e.g.) may be arranged so that the area required in one or more dimensions may be minimized.

Integrated circuit having pads and input/output (I/O) cells

A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.

Solderable metal finish for integrated circuit package leads and method for forming

A semiconductor die is housed in a package body. Leads, which are electrically coupled to the semiconductor die, extend from the package body and are for connecting to a printed circuit board or other device. The leads are coated with a material that protects the leads from oxidation. The coating is compatible with solder techniques that are commonly used to attach packaged semiconductors to a printed circuit board. In some examples, the coating is removable, after drying, at temperatures below one hundred eighty degrees Celsius. This allows for solder processes, which are typically at least 180&#xb0; C., to remove the coating thereby exposing the leads, which has been protected from oxidation, so that it can be soldered to the printed circuit board. In some examples, the coating material includes an organic material. In some examples, the coating material is an organic solderability preservative (OSP).

Packaged semiconductor with coated leads and method therefore

To mitigate mold encapsulant bleeding and solder mask cracking in plastic semiconductor packages, a damming structure constructed from metal traces is formed in-line with the encapsulant perimeter. In one embodiment, each damming trace is connected to only one electrical trace, which includes a bonding connection, a signal portion and a plating portion. The damming traces can consist of one trace that is wider than any of the signal traces or multiple rows of traces, for example. The result is a reduction in mold encapsulant bleeding and, thus, an eradication of the processes performed to clean the bleeding.

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Austin, TX, United States of America

Nhat Dinh Vo