Unisys Corporation

Nguyen T Tran

John Steven Kuslak

Kenneth L Engelbrecht

Lawrence R Fontaine

An apparatus for and method of providing a data processing system that delays the writing of an architectural state change value to a corresponding architectural state register for a predetermined period of time. This may provide the instruction processor with enough time to determine if the architectural state change is valid before the architectural state change is actually written to the appropriate architectural state register.

Delayed state writes for an instruction processor

A method and apparatus for efficiently requesting the instruction processor to store its state information directly to main memory storage is provided by a single instruction command. An advantage is a performance improvement over the prior art since the time-consuming tasks of transferring Local Area Network (LAN) messages and scanning the instruction processor are eliminated. An additional advantage is a savings in computer time since the System Control Facility (SCF) and Network Interface Module (NIM) are not required to store the instruction processor state information. Yet another advantage is large amounts of additional hardware are not required. The same control logic used to generate the o-cache jump-history entry is used to generate the store software instrumentation package instruction which requests the instruction processor to store its state information directly to main memory storage.

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Plymouth, MN, United States of America

Nguyen T Tran