Advanced Micro Devices Corporation

Lattice Semiconductor Corporation

Nguyen Duc Bui

Van Hung Pham

Farrokh Kia Omid-Zohoor

Donald L Wollesen

John T Yue

Binh Ly

Scott Zheng

Chenming Hu

Effiong Etukudo Ibok

Amit P Marathe

John R Hauser

Richard C Smoak

Dainius A Vidmantas

Khaled Z Ahmed

Michael Anthony Niederhofer

Donggun Park

A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

Multi-time programmable non-volatile memory cell

A semiconductor device having a metallized interconnect structure includes a conductor having an upper contact surface and an edge surface depending from the upper contact surface. An opening in an insulating layer overlying the conduct exposes at least a portion of the upper contact surface and at least a portion of edge surface. A liner material covers the edge surface and a portion of the upper contact surface exposed by the opening. An electrically conductive material resides within the opening and is separated from the edge surface by the liner material. A method for fabricating the metallized contact structure includes the deposition and anisotrophic etching of a liner material that is differentially etchable with respect to the insulating layer overlying the conductor. By covering the edge surface of the conductor, a metallized contact structure is provided that can be reliably fabricated using zero-overlap design tolerances.

Semiconductor device having metallized interconnect structure and method of fabrication

An embodiment of the memory cell for an EEPROM device may comprise a trench coupling capacitor wherein the coupling oxide of the coupling capacitor is formed only in the trench (i.e., such that coupling occurs only in the trench). In addition, a first portion of a floating gate of the memory cell is formed in the trench to function as a part of the coupling capacitor as well as a floating gate. A floating gate second portion is electrically connected to the first portion. A control gate is connected to a doped region of the substrate and a thin tunnel dielectric physically separates the floating gate second portion from the coupling oxide layer and from the doped region of the substrate.

EEPROM cell with trench coupling capacitor

An apparatus and method used in extracting polysilicon gate doping from C&minus;V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

MOSFET test structure for capacitance-voltage measurements

The as-deposited thickness of at least one of the oxide layers of a composite ONO dielectric film between a floating gate and a control gate of a non-volatile semiconductor device is deposited to a sufficient thickness such that, after the top oxide layer is cleaned, the control gate is spaced apart from the floating gate a distance corresponding to at least a minimum design data retention. Deposition is facilitated by forming one or more oxide layers at a thickness greater than the design rule by employing a relatively high dielectric constant material for the oxide layer or layers, such as aluminum oxide, titanium oxide or tantalum oxide. In this way, the capacitance of the ONO film between the floating gate and the control gate is maintained per design rule, avoiding a change in operating voltage. Embodiments include depositing a relatively thick top oxide layer to enable thorough cleaning without adversely reducing the total thickness of the ONO stack and, hence, achieving design data retention.

Method of forming a composite interpoly gate dielectric

A method and apparatus for monitoring and controlling integrated circuit devices-under-test (DUTS). A preferred embodiment includes a computer based controller, a temperature control module, a power supply controller, a chamber interface module, a driver card and a DUT board. The computer-based controller responding to preprogrammed instructions (software) operates and coordinates the temperature control module, the chamber interface module, the power supply controller, and the driver card. The driver card, receiving commands and data from the computer-based controller, sends and receives a number of signals to and from the DUTs on the DUT board. These signals include voltage sources for operating the DUTs, a load voltage, DC current sources for setting duty and frequency cycles, switch signals, voltage measurement signals, and resistance measurement signals. The DUT board is a printed circuit board for holding a number of DUTs. Each of the DUTs is an integrated circuit containing one or more sets of circuitry for testing specifically designed test structures.

Method and apparatus for reliability testing of integrated circuit structures and devices

An interconnection test structure for evaluating more accurately and reliably electromigration characteristics is provided. The test structure includes an elongated metal test conductor having a first end and a second end, small extension metal conductors connected to the first end and the second end of the test conductor, and a plurality of vias disposed in the small extension metal conductors adjacent the first end and the second end of the test conductor. As a result, the current density of the plurality of vias is made to be less than the current density of the test conductor.

Interconnection device for low and high current stress electromigration and correlation study

A categorization of a particular semiconductor wafer based on void size is obtained from sigma data and T0.1% failure data that has been obtained from wafers subjected to isothermal testing. The sigma data and the T0.1% failure data for the particular wafer is compared to stored data corresponding to ranges for sigma and T0.1% data for each of a plurality of void categories, and the particular wafer is categorized based on the stored data. The T0.1% failure data is computed based on a T50% failure data and the sigma value, so that small sample sizes can be utilized to obtain the stored data.

Sensitive technique for metal-void detection

Methods are provided to increase the process control during the fabrication of the control gate configuration in a non-volatile memory semiconductor device. The methods effectively smooth out the top surface of the control gate layer, which allows for a subsequently formed silicide layer to be formed on the control gate layer without significant surface depressions. Significant surface depressions in either the control gate layer or the silicide layer can lead to cracking of the silicide layer during subsequent thermal processing of the semiconductor device. Thus the disclosed methods prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.

Methods for forming a control gate apparatus in non-volatile memory

A method for detecting damage in a plurality of transistors includes measuring at least one characteristic of the plurality of transistors, applying a constant voltage of a predetermined voltage level for a predetermined period of time, and re-measuring the at least one characteristic of the plurality of transistors, wherein a change in the at least one characteristic indicates damage to the plurality of transistors. In one aspect, the predetermined voltage level is about 9 MV/cm, and the predetermined period of time is about 1 second. In a further aspect, measuring at least one characteristic includes measuring threshold voltage, and the change in the at least one characteristic includes a shift in the threshold voltage. In another embodiment, a method for monitoring damage in unprotected plurality of transistors during wafer fabrication includes performing a test sequence including applying a constant voltage of a predetermined voltage level for a predetermined period of time, and utilizing the test sequence in-line with the wafer fabrication. In addition, detecting damage further includes programmably controlling the steps of performing and utilizing during wafer fabrication, wherein programmably controlling is performed with a computer system.

Detection of process-induced damage on transistors in real time

Techniques for measuring process induced damage, such as damage experienced during plasma etching or ion implementation, utilize a differential amplifier having multi-layer antennas (capacitors) of different sizes formed on respective inputs. Measurement of .DELTA.Ids (the difference between Ids.sub.1 and Ids.sub.2 off a MOSFET of the differential pair) or .DELTA.Idlin provides a sensitive and accurate measure of process induced damage. The techniques can be applied to monitor process induced damage while the manufacturing process is ongoing or as a measure of quality of the finished product.

Sensitive method of evaluating process induced damage in MOSFETs using a

Interconnect via structures in a semiconductor integrated circuit having low resistance. The interconnect via structures connect metal layer structures in the semiconductor device and extend down at least one side of the metal layer structures. The interconnect via structures can extend down a second side of the metal layer structures and can extend down the end of the metal layer structures. The interconnect via structures extend beyond the sides and the end of the metal layer structures by a distance u where u is 1/4 to 1/2 F, where F is a feature of the design rule being used to manufacture the semiconductor device.

Intergrated circuit interconnect via structure having low resistance

A substantially constant current is conducted in a first direction through an interconnect structure having a barrier layer to determine the lifetime of the structure in the first current direction. A substantially identical current is conducted in a second direction through a substantially identical interconnect structure to determine the lifetime of the structure in the second current direction. These tests are repeated for identical structures but having different barrier layer thicknesses. The results of these lifetime tests are compared to determine the barrier layer's effect on electromigration in the structure, which can be used to design the barrier layer to optimize the structure's lifetime and speed.

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San Jose, CA, United States of America

Nguyen Duc Bui