Synopsys, Inc.

Cadence Design Systems, Inc.

Ngai Ngai William Hung

Dhiraj Goswami

Yong Liu

Michael Patrick Zimmer

Jasvinder Singh

Qiang Qiang

Guillermo R Maturana

Rajarshi Mukherjee

Soe Myint

Leonid Alexander Broukhis

Jason Chung-Shih Chen

Lingyi Liu

Sitanshu Seth

Aijun Hu

Na Xing

Amiya Ranjan Satapathy

Implementations may include a method of accelerated modification of an emulation processor system, by loading, by a first emulation processor, a first portion of processor instructions into one or more registers of the first emulation processor, in response to a selection of a first programming mode associated with the first emulation processor, and loading, by a second emulation processor operatively coupled with the first emulation processor, a second portion of the processor instructions into one or more registers of the second emulation processor, in response to a selection of a first programming mode associated with the second emulation processor.

Systems and methods for distributed and parallelized emulation processor configuration

A system and a method are disclosed for emulating a design of an electronic circuit. One or more field programmable gate array (FPGA) overlays are programmed to implement a first set of logic elements of the design of the electronic circuit. A second set of logic elements of the design of the electronic circuit is implemented in one or more FPGAs. The FPGA overlays implementing the first set of logic elements and the FPGAs implementing the second set of logic elements are interconnected to each other. The design of the electronic circuit is then tested using the interconnected FPGA overlays and the FPGAs.

FPGA implementation interleaved with FPGA overlay architectures for emulation

An approach is described for a method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth. According to some embodiments, this approach includes providing a systolic array that includes processing elements which each have some number of storage elements for storing weights. For example, the weights can be reused for different data sets by identifying/capturing a current state of the storage elements, generating a plan to transition to a target state of those storage elements, and application of the transition plan such that weights that are already stored in those storage elements can be reused and/or relocate. This lowers the bandwidth requirements for weight memory by allowing weights that have previously been read into the systolic array to be reused.

Method, product, and apparatus for a machine learning process using weight sharing within a systolic array having reduced memory bandwidth

An approach includes receiving a machine learning processing job, executing the machine learning processing job using parallel processing of multiple output pixels each cycle by walking data across processing elements with broadcast weights within regions and executing parallel multiplication operations, and generating an output indicating whether the machine learning processing job was successful or failed. In some embodiments, a schedule of actions is generated for respective machine learning processing jobs. The schedule of actions may include any of a plurality of shift operations in a many to many arrangement or a one to many arrangement, shifting data across region boundaries, fetching data and weights from a memory and distribution thereof to a plurality of regions (e.g., weights are distributed to respective weight memories which subsequently broadcasts those weights in a specified order based on a schedule of actions, and where data is distributed to respective processing elements).

Method, product, and apparatus for a multidimensional processing array for hardware acceleration of convolutional neural network inference

An approach includes a method, product, and apparatus for dynamically removing sparse data on a pixel by pixel basis. In some embodiments, a machine learning processing job is received. The machine learning processing job is then executed on a pixel by pixel basis by selecting non-zero data values for input into a systolic array, wherein sparse data is not selected for input into the systolic array. Subsequently, a message is generated that provides an indication of whether the execution completed successfully. In some embodiments, the machine learning processing job comprises at least a plurality of multiply and accumulate operations. In some embodiments, at least one data value equal to zero for the machine learning processing job is not input into a systolic array. In some embodiments, a plurality of weights are input into a plurality of columns for each cycle.

Method, product, and apparatus for a machine learning process leveraging input sparsity on a pixel by pixel basis

An approach is described for a method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights. This approach includes a method, product, and apparatus for dynamically rearranging input data to move sparse data to a location such that computations on the sparse data might be avoided when executing a machine learning processing job. For example, sparse data within each row of the input matrix can be moved to the end of each corresponding row. When the input data is folded to fit the array, that sparse data might be at least partially contained within a fold that comprises only sparse data and possibly filler data. In such an event, computations on the fold are unnecessary and are avoided. In some embodiments, the approach includes dynamically rearranging a weight matrix to maintain a correspondence between the input data and the weights.

Method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights

An approach includes identification of a machine learning model for processing and generating an ordered set of weights with varying precisions and metadata that specifies where those values can be found in order to allow the identification of weights needed during processing. In a first embodiment, the variable precision weights are separated into different memory segments where each segment has weights of only a single precision. In a second embodiment, the variable precision weights are provided in a memory where weights of different precisions are intermingled, and those weights are identified using a sequence of pairs of data representing a number of weights with the same precision and the precision of those weights. In some embodiments, both the first and second embodiments are combined, where some segments contain weights with only a single precision and at least one segment stores weights with different precisions within a respective segment.

Method, product, and apparatus for variable precision weight management for neural networks

Computer-implemented techniques are disclosed for verifying circuit designs using subgraph caching. A device under test (DUT) is modeled as a graph. The graph is partitioned into one or more subgraphs and problems are generated for each subgraph. Graph and subgraph problem generation is repeated numerous times throughout the verification process. Problems and sub-problems are generated and solved. When a subgraph problem is solved, the problem's variables, values, and information can be stored in a cache. The storage can be based on entropy of variables used in the graph and subgraph problems. The subgraph problem storage cache can be searched for previously stored problems which match another problem in need of a solution. By retrieving subproblem variables, values, and information from the cache, the computational overhead of circuit design verification is reduced as problems are reused. Caching can be accomplished using an information theoretic approach.

Information theoretic subgraph caching

Methods and apparatuses are described for assigning random values to a set of random variables so that the assigned random values satisfy a set of constraints. A constraint solver can receive a set of constraints that is expected to cause performance problems when the system assigns random values to the set of random variables in a manner that satisfies the set of constraints. For example, modulo constraints and bit-slice constraints can cause the system to perform excessive backtracking when the system attempts to assign random values to the set of random variables in a manner that satisfies the set of constraints. The system can rewrite the set of constraints to obtain a new set of constraints that is expected to reduce and/or avoid the performance problems. The system can then assign random values to the set of random variables based on the new set of constraints.

Optimizing constraint solving by rewriting at least one bit-slice constraint

Configuring a hardware verification system includes receiving first data representing a first integrated circuit design configured to operate via a first clock signal derived from a second clock signal and a third signal generated by the second clock signal. The computer transforms the first data into second data representing a second design that includes functionality of the first design. The transformation replaces the first clock signal with the second clock signal. A first Boolean function is defined by first and second values of the third signal corresponding to a first transition of the second clock signal being in a same direction as a transition of the first clock signal. A second Boolean function is defined by the first and second values of the third signal corresponding to a second transition of the second clock signal being in a direction opposite to the associated transition of the first clock signal.

Formal method for clock tree analysis and optimization

Disclosed is a resettable memory device including a memory unit, a reset status indicator circuit, a logic sampling circuit, and a multiplexer for performing a reset function. The memory unit includes cells for storing states of signals in a design under test. The reset status indicator stores states of indicators indicating whether corresponding cells should be reset or not. Responsive to the reset status indicator indicating that the value of the cell should not be reset, the multiplexer receives the value stored in the cell and outputs the retrieved value from the cell. Responsive to the reset status indicator indicating that the value of the cell should be reset, the multiplexer outputs a reset value instead of the value stored in the cell. The reset value may be changed by the logic sampling circuit at different time periods or certain logic conditions, and output through the multiplexer.

Generalized resettable memory

Computer-implemented techniques are disclosed for verifying circuit designs using dynamic problem generation. A device under test (DUT) is modeled as part of a test bench where the test bench is a random process. A set of constraints is solved to generate stimuli for the DUT. Problem generation is repeated numerous times throughout a verification process with problems and sub-problems being generated and solved. When a problem is solved, the problem structure can be stored in a cache. The storage can be based on entropy of variables used in the problem. The problem storage cache can be searched for previously stored problems which match a current problem. By retrieving a problem structure from cache, the computational burden is reduced during verification. Problems can be multi-phase problems with storage and retrieval of problem structures based on the phase level. Caching can be accomplished using an information theoretic approach.

Information theoretic caching for dynamic problem generation in constraint solving

A design verification workstation contains both debug and constraint solver capabilities during simulation of a design under test. The design verification workstation is configured to allow the user to debug constraints, stop the constraint solver, navigate problems and variables, and make modifications on-the fly during the simulation to constraint information. Additionally, in some embodiments, the design verification workstation may allow a user to use a constraint solver to experiment if the modifications will lead to desired test stimulus. Since this debug process happens during simulation, users do not need to recompile the test case. Additionally, once a user is satisfied with the modifications made to the simulation, the modification could be saved for future usage.

Development and debug environment in a constrained random verification

Optimizing constraint solving by rewriting at least one modulo constraint

Methods and apparatuses are described for identifying inconsistent constraints. During operation, a system can receive a set of constraints, wherein each constraint is defined over one or more random variables from a set of random variables. If an inconsistency or conflict is detected while solving the set of constraints, the system can identify a phase in a series of phases of the constraint solver where the inconsistency was detected. The system can then try to solve different subsets of the set of constraints to identify smaller subsets of the set of constraints that contain the inconsistency. When the system tries to solve a subset of the set of constraints, the system can determine whether or not an inconsistency is detected in the identified phase while solving the subset of the set of constraints. Next, the system can report the smallest subset of inconsistent constraints that was found to a user.

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San Jose, CA, United States of America

Ngai Ngai William Hung