Advanced Micro Devices Corporation

Spansion Llc.

Nga-Ching Wong

Sameer S Haddad

Timothy J Thurgate

Mark T Ramsbey

Mark W Randolph

Emmanuil Lingunis

Richard M Fastow

Darlene G Hamilton

Yue-Song He

Yi He

Kashmir S Sahota

Tazrien Kamal

Ashot Melik-Martirosian

Jeffrey P Erhardt

Weidong Qian

Concetta E Riccobene

Edward Franklin Runnion

Tim Thurgate

The present invention provides a method of fabricating a doped semiconductor region comprising selectively implanting a first impurity to form a shallow heavily doped region. The method further comprises selectively implanting the first impurity to also form a deep more heavily doped region, disposed laterally within the shallow heavily doped region and vertically within and below the shallow heavily doped region. In an optional feature of the present invention, the method further comprises selectively implanting a second impurity, wherein the doping profile of the deep more heavily doped region is graded.

Method for manufacturing a double bitline implant

A method and structure is provided for an integrated circuit with a semiconductor substrate having an opening provided therein. A doped high conductivity region is formed from doped material in the opening and a diffused dopant region proximate the doped material in the opening. A structure is over the doped high conductivity region selected from a group consisting of a wordline, a gate, a dielectric layer, and a combination thereof.

Semiconductor device with high conductivity region using shallow trench

The present invention pertains to implementing a lightly doped channel (LDC) implant in fashioning a memory device to improve Vt roll-off, among other things. The lightly doped channel helps to preserve channel integrity such that a threshold voltage (Vt) can be maintained at a relatively stable level and thereby mitigate Vt roll-off. The LDC also facilitates a reduction in buried bitline width and thus allows the bitlines to be brought closer together. As a result more devices can be formed or 'packed' within the same or a smaller area.

LDC implant for mirrorbit to improve Vt roll-off and form sharper junction

A charge trapping dielectric memory cell array comprises a plurality of parallel bit lines implanted within the lightly doped substrate. The parallel bit lines define a plurality of channel regions spaced there between and form a semiconductor junction there with. A plurality of parallel and spaced apart word lines are positioned above the surface of the substrate and separated from the substrate by a charge trapping dielectric. The plurality of parallel word lines are perpendicularly positioned with respect to the bit lines. Each channel region comprises a central counter doped channel region adjacent to a top surface of the substrate and vertically extending into the channel region to a depth less than the bit line depth and being spaced from each semiconductor junction by a pocket region.

Dielectric memory cell structure with counter doped channel region

Embodiments of the present invention include a method for manufacturing a transistor comprising forming a gate conductor above a semiconductor substrate; forming a lightly doped implant region within the substrate, wherein the lightly doped implant region is substantially on the source side of the transistor; and forming a counter doping implant region within the substrate, wherein the counter-doping implant region is substantially on the drain side and wherein the counter-doping reduces the net channel impurity concentration on the drain side.

Structure and method to reduce drain induced barrier lowering

A lateral doped channel. A first doping material is implanted substantially vertically into a region adjacent to a gate structure. A diffusion process diffuses the first doping material into a channel region beneath the gate structure. A second doping material is implanted substantially vertically into the region adjacent to a gate structure. The second implantation forms source/drain regions and may terminate the channel region. The channel region thus comprises a laterally non-uniform doping profile which beneficially mitigates the short channel effect and is highly advantageous as compensation for manufacturing process variations in channel length.

Lateral doped channel

A method and system for substrate bias for programming non-volatile memory. A bias voltage is applied to a deep well structure under a well comprising a channel region for a non-volatile memory cell. During programming, a negative bias applied to the deep well beneficially creates a non-uniform distribution of electrons within the channel region, with an abundance of electrons at the surface of the channel region. The application of additional bias voltages to a control gate and a drain may cause electrons to migrate from the channel region to a storage layer of the non-volatile memory cell. Advantageously, due to the increased supply of electrons at the surface of the channel region, programming of the non-volatile cell takes place faster than under the conventional art.

Substrate bias for programming non-volatile memory

A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell

Embodiments of the present invention relate to a method for fabricating a Vss line in a memory device, which comprises: forming a plurality of memory cells above a semiconductor substrate, forming a channel between two of the memory cells, forming an oxide/nitride/oxide stack above the memory cells and the channel, removing a portion of the oxide/nitride/oxide stack between the memory cells to expose the semiconductor substrate, removing the oxide/nitride/oxide stack above the gates of the memory cells, forming a plurality of source regions in the substrate between the memory cells, forming a poly-silicon layer above the memory cells and the channel to connect to the source regions, and removing a sufficient portion of the poly-silicon layer to form a Vss line.

Method for forming a dielectric spacer in a non-volatile memory device

The present invention is a method for fabricating a memory device. In one embodiment, a first impurity concentration is deposited in a channel region of a memory device. A second impurity concentration, which overlies the first impurity concentration, is then created in the channel region. Finally, a memory array is fabricated upon the channel region. The memory array overlies the first impurity concentration and the second impurity concentration.

Method for reducing drain induced barrier lowering in a memory device

A method is provided for accurately determining the junction depth of silicon-on-insulator (SOI) devices. Embodiments include determining the junction depth in an SOI device under inspection by measuring the threshold voltage of its &ldquo;bottom transistor&rdquo; formed by its source and drain regions together with its substrate acting as a gate. The threshold voltage of the bottom transistor of an SOI device varies with its junction depth in a predictable way. Thus, the junction depth of the inspected device is determined by comparing its bottom transistor threshold voltage with the bottom transistor threshold voltage of corresponding reference SOI devices of known junction depth to find a match. For example, simulated SOI devices with the same characteristics as the inspected device, whose junction depth and bottom transistor threshold voltages have been previously calculated, are used as a &ldquo;reference library&rdquo;. If the bottom transistor threshold voltage of the inspected device has about the same value as that of a particular one of the reference devices, then the inspected device has the junction depth of that particular reference device. Thus, junction depth of the inspected SOI device is accurately determined by a simple electrical measurement of threshold voltage.

Growing community of inventors

San Jose, CA, United States of America

Nga-Ching Wong