Chartered Semiconductor Manufacturing Ltd (corporation)

Ng Chit Hwei

Sanford Chu

Shao Kai

Lap Chan

Purakh Raj Verma

Zheng Jia Zhen

Ho-Chaw Sing

Tjoa Tjin Tjin

Bao Guang Wen

A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.

Method to enhance inductor Q factor by forming air gaps below inductors

Methods for forming a metal-insulator-metal (MIM) capacitor using an organic anti-reflective coating (ARC) are described. The first electrode of the MIM capacitor is formed from a first metal layer. The organic ARC is applied, and the second electrode of the MIM capacitor is formed from a second metal layer. The organic ARC is then removed using a nominal clean technique. Because the organic ARC is removed, the performance of the MIM capacitor is improved. Specifically, the breakdown voltage of the MIM capacitor increases and the leakage current decreases.

Method for forming a MIM (metal-insulator-metal) capacitor

A first and second damascene copper interconnect plug are created over the surface of a substrate. A MIM capacitor, which is aligned with the second damascene copper interconnect plug, is created by a one-time etch of a stack of layers comprising Ta/capacitor dielectric/Ta. Copper interconnects are then created aligned with the MIM capacitor and the second damascene interconnect plug.

Metal sandwich structure for MIM capacitor onto dual damascene

A new method for forming a dual-metal gate CMOS transistors is described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A nitride layer is deposited overlying a gate dielectric layer and patterned to form a first dummy gate in each of the active areas. First ions are implanted to form source/drain regions in each of the active areas not covered by the first dummy gates. The first dummy gates are isotropically etched to form second dummy gates thinner than the first dummy gates. Second ions are implanted to form lightly doped source/drain regions in each of the active areas not covered by the second dummy gates. Dielectric spacers are formed on sidewalls of the second dummy gates and the source/drain regions are silicided. The second dummy gates and spacers are removed. A first metal layer is deposited overlying the substrate and patterned to form a first metal gate in one of the NMOS and PMOS active areas. An oxide layer is deposited overlying the substrate and the first metal gate. The oxide layer is polished back to the metal gate. A via is opened through the oxide layer to the substrate in the other one of said NMOS and PMOS areas. A second metal layer is deposited within the via opening and polished back to the oxide layer to form a second metal gate in the other one of the NMOS and PMOS area to complete formation of dual-metal CMOS gates.

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Singapore, Singapore

Ng Chit Hwei