Intel Corporation

Hewlett-Packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Digital Equipment Corporation

Nevine Nassif

Gerald S Pasdast

Carleton L Molnar

Krishnakanth Venkata Sistla

Ankush Varma

Yen-Cheng Liu

Dheeraj R Subbareddy

George Zacharias Chrysos

Vedaraman Geetha

Mahesh K Kumashikar

Jeffrey D Chamberlain

William R Halleck

James Arthur Farrell

Tejpal Singh

Srikanth Nimmagadda

John R Ayers

Siva Soumya Eachempati

Nicholas Lee Rethman

Harry Ray Fair, Iii

Madhav Desai

Roy Badeau

Gill Watt

Dale Hayward Hall

Johanna M Swan

Adel A Elsherbini

Shawna M Liff

Mark T Bohr

Dmitri E Nikonov

Tanay Karnik

Wilfred Gomes

Krishna Bharath

Julien Sebot

Neelam Chandwani

Robert J Munoz

Joel J Grodstein

Wesley D McCullough

William J Grundmann

Udi Sherel

Nicholas L Rethman

Leonard M Neiberg

A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

Fine-grained disaggregated server architecture

Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

Multiple dies hardware processors and methods

Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.

Functionally redundant semiconductor dies and package

The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Timing verifier for MOS devices and related method

A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

Method and apparatus for performing timing verification of a circuit

A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error. This shifting increases the total error between the compressed data and reality by more than is acceptable in current simulations. The present method approximates the data curve with piecewise linear segments all of which are on a selected side of the curve, for example the late side. This avoids increasing the error between the data curve and the stored approximation due to shifting of the stored data to ensure that all points are on the selected side.

Method to compress a piecewise linear waveform so compression error occurs on only one side of the waveform

A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.

Method and apparatus for estimating elmore delays within circuit designs

The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.

Method and apparatus for modeling gate capacitance of symmetrically and asymmetrically sized differential cascode voltage swing logic (DCVSL)

A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

Pruning of short paths in static timing verifier

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Arlington, MA, United States of America

Nevine Nassif