Analog Devices,inc.

Nevena Rakuljic

Carroll Clifton Speir

Eric Otte

Jeffrey Paul Bray

Milutin Pajovic

Gabriele Manganaro

Tao Yu

Siddharth Devarajan

Corey Petersen

Omer Tanovic

Xiao Yu Wang

Gregory Patrick Davis

Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. A digital nonlinearity correction (NLC) can be implemented in a receiver signal chain having an ADC. Digital NLC can be designed as a drop in signal preconditioner for existing RF ADC wideband receiver signal chains. A unique equalizer can compensate for a variety of mixer spurs. Accordingly, digital NLC can correct nonlinearities due to mixers and any amplifiers preceding or following the ADC, potentially improving receive chains performance by 15-25 dB. Such a digital NLC solution can be particularly beneficial in defense and instrumentation applications which demand the greatest performance.

Digital correction techniques for wideband receiver signal chain nonlinearities

Non-idealities of input circuitry of a receiver signal chain can significantly degrade the overall performance of the receiver signal chain. To meet high performance requirements, the input circuitry is typically implemented with power hungry circuitry in a different semiconductor technology from the analog-to-digital converter that the input circuitry is driving. With suitable optimization techniques, performance requirements on the input circuitry can be reduced while meeting target performance of the receiver signal chain. Specifically, optimization techniques can compensate for input frequency-dependent properties and/or amplitude-dependent properties of the input circuitry. In some cases, reducing performance requirements on the input circuitry means that the input circuitry can be implemented in the same semiconductor technology as the analog-to-digital converter.

Receiver signal chains with low power drivers and driver optimization

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Signal path linearization

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Microprocessor-assisted calibration for analog-to-digital converter

Randomly sampling reference ADC for calibration

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San Diego, CA, United States of America

Nevena Rakuljic