Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Intel Ndtm US LLC

Netra Mahuli

Aliasgar S Madraswala

Ali Khakifirooz

Yogesh B Wakchaure

Shantanu R Rajwade

Tzu-Ning Fang

Rezaul Haque

Narayanan Ramanan

Camila Jaramillo

Matin Amani

Binh Ngo

Ahsanur Rahman

John Egler

Bayan Nasri

Dhanashree R Kulkarni

Seong Je Park

Bharat Pathak

Naveen Prabhu Vittal Prabhu

Renjie Chen

A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

Memory cell sensing circuit with adjusted bias from pre-boost operation

Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.

Independent multi-page read operation enhancement technology

An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

Automatic read calibration operations

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Folsom, CA, United States of America

Netra Mahuli