Bar-ilan University

Netanel Shavit

Joseph Shor

Yitzhak Schifmann

Edison Ramiro Taco Lasso

Inbal Stanger

A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.

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Ramla, Israel

Netanel Shavit