Marvell International Limited

Mediatek Singapore Pte. Ltd.

Neric Fong

Sang Won Son

Bo Wang

Lydi Smaini

Bing Xu

Siu-Chuang Ivan Lu

Ankush Goel

Wei-Cheng Liu

Chao Lu

Chunwei Chang

Terry W Chen

A gain asymmetry characterizing circuit for determining characteristics of gain asymmetry possessed by a transmitter includes a baseband loopback path, a test signal generating unit and a gain asymmetry measuring unit. The baseband loopback path is coupled to a baseband node on a first transmission path of the transmitter. The test signal generating unit is arranged to generate a first differential baseband test signal pair to the first transmission path. The first differential baseband test signal pair includes a first baseband signal and a second baseband signal. During a first period, the first baseband signal and the second baseband signal are fed into a positive input node and a negative input node of the first transmission path, respectively. During a second period, the second baseband signal and the first baseband signal are fed into the positive input node and the negative input node of the first transmission path, respectively.

Gain asymmetry characterizing circuit and method for determining characteristics of gain asymmetry possessed by transmitter

A communication unit includes at least one divider module arranged to receive a radio frequency (RF) signal and output a divided representation of the RF signal, and a plurality of sliced RF modules. Each of the plurality of sliced RF modules includes: an input for receiving a clock signal; a timing synchronization module arranged to receive the divided representation of the RF signal and synchronize the divided representation of the RF signal to the clock signal, across the plurality of sliced RF modules; and at least one logic module operably coupled to the timing synchronization module and arranged to receive the clock signal and a synchronized output from the timing synchronization module. A combiner port is arranged to couple a number of synchronized outputs from the plurality of sliced RF modules.

Communication unit and sliced radio frequency module therefor

A frequency and phase conversion circuit and wireless communication unit for supporting a plurality of different duty cycles is described. The frequency and phase conversion circuit comprises: a local oscillator module comprising a plurality of frequency conversion modules arranged to receive at least one input clock signal wherein a plurality of phases of the at least one input clock signal are selectable to support a plurality of different duty cycle clock signals; and at least one frequency conversion module comprising a plurality of mixer arrangements configured to receive at least one baseband input signal and the selected plurality of phases of the at least one input clock signal and output a frequency and phase converted representation of the at least one baseband input signal, wherein at least one of the plurality of mixer arrangements is re-used in a plurality of the selectable supportable duty cycles.

Frequency and phase conversion circuit, wireless communication unit, integrated circuit and method therefor

One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33&#x2153; percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33&#x2153; percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals.

High linearity mixer using a 33% duty cycle clock for unwanted harmonic suppression

The disclosure can provide methods and systems for autocalibrating a transceiver. The method can include upconverting a bandpass input signal by mixing the bandpass input signal with a first local oscillator signal to form an initial transmitter signal. The initial transmitter signal can be looped back to a receiver and downconverted with a second local oscillator signal having a frequency that is different from the first local oscillator to form an intermediate frequency signal. At least one of a gain and a phase of the transmitter can be adjusted based on a transmitter image sideband of the intermediate frequency signal to generate a calibrated transmitter signal having minimized transmitter image sideband.

On-chip I-Q imbalance and LO leakage calibration for transceivers

The present invention provides for a circuit with slicing wherein a gain asymmetry variation is decreased across the plurality of mixer slices. In one or more embodiments, a calibration unit can be provided to determine the characteristics of gain asymmetry variation; and a digital compensation unit can be provided to adjust the gain of the circuit over frequency.

Circuit and transmitter for reducing transmitter gain asymmetry variation

Circuits, architectures, a system and methods for providing on-chip gain calibration. The circuit generally includes a receiver comprising (i) a resistor on a semiconductor substrate, the resistor configured to provide a signal having a noise component that varies with temperature, and (ii) an amplifier circuit on the semiconductor substrate coupled to the resistor, the amplifier circuit configured to receive the signal and provide a second signal having an amplitude greater than the first signal. The architectures and/or systems generally include those that embody one or more of the inventive concepts disclosed herein. The method generally includes (i) providing a noise signal from a resistor to an amplifier, the resistor being on a common semiconductor substrate with the amplifier, (ii) determining a resistance value of the resistor, (iii) determining an impedance at an input of the amplifier, and (iv) determining a gain of the amplifier.

Method and apparatus for respectively calibrating a gain of a plurality of amplfiers of an amplfier circuit

A mixer circuit is disclosed. The mixer circuit comprises a plurality of mixer elements, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle of 33&#x2153; percent. Outputs signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. The third-order harmonic of the mixer is eliminated by using mixer which uses voltage sampling on non-overlapping clocks and thereby achieves high linearity. The mixer circuit is further expanded to remove the I-Q image and even order harmonics.

Growing community of inventors

Santa Clara, CA, United States of America

Neric Fong