Micron Technology Incorporated

Round Rock Research, LLC

Neo Yong Loo

Chia Yong Poo

Boon Suan Jeung

Chua Swee Kwang

Low Siu Waf

Chan Min Yu

Eng Meow Koon

Zhou Wei

Huang Shuang Wu

Ser Bok Leng

So Chee Chung

Ho Kwok Seng

Yong Poo Chia

Suan Jeung Boon

Swee Kwang Chua

Hu Kwok Seng

Low Slu Waf

Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Apparatus and method for packaging circuits

Through vias in a substrate are formed by creating a trench in a top side of the substrate and at least one trench in the back side of the substrate. The sum of the depths of the trenches at least equals the height of the substrate. The trenches cross at intersections, which accordingly form the through vias from the top side to the back side. The through vias are filled with a conductor to form contacts on both sides and the edge of the substrate. Contacts on the backside are formed at each of the trench. The through vias from the edge contacts. Traces connect bond pads to the conductor in the through via. Some traces are parallel to the back side traces. Some traces are skew to the back side traces. The substrate is diced to form individual die.

Wafer level packaging

Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

Castellation wafer level packaging of integrated circuit chips

Method for fabricating packaged die

A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.

Support elements for semiconductor devices with peripherally located bond pads

A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods

A semiconductor device package is disclosed which is substantially die-sized with respect to each of the X, Y and Z axes. The package includes outer connectors that are located along at least one peripheral edge thereof and that extend substantially across the height of the peripheral edge. Each outer connector is formed by severing a conductive via that extends substantially through a substrate blank, such as a silicon wafer, at a street located adjacent to an outer periphery of the semiconductor device of the package. The outer connectors may include recesses that at least partially receive conductive columns protruding from a support substrate therefor. Assemblies may include the packages in stacked arrangement, without height-adding connectors.

Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices

Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages

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Singapore, Singapore

Neo Yong Loo