Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

Uwiz Technology Co., Ltd.

Winbond Electronics Corporation

United Microelectric Corp.

Neng-Kuo Chen

Clement Hsingjen Wann

Sey-Ping Sun

Gin-Chen Huang

Teng-Chun Tsai

Yi-An Lin

Chien-Chung Huang

Cheng-Yuan Tsai

Meng-Chun Chang

Sung-Li Wang

Chia-Jung Hsu

Kuo-Hwa Tzeng

Ching-Hong Jiang

Chin-Hsiang Lin

Chih-Hsin Ko

Chun-Wei Chang

Ding-Kang Shih

Chen-Feng Hsu

Hau-Yu Lin

Wen-Han Hung

Song-Yuan Chang

Yun-Lung Ho

Shao-Ta Hsu

Yi-Tang Lin

Hsiu-Lien Liao

Chun Hsiung Tsai

Yu-Lien Huang

Ling-Yen Yeh

Shyh-Fann Ting

Cheng-Tung Huang

Jeff J Xu

Chi-Yuan Shih

Tzyy-Ming Cheng

Kun-Hsien Lee

Yen-Chun Huang

Li-Shian Jeng

Ta-Chun Ma

Li-Chi Yu

Tung Ying Lee

Cheng-Ta Wu

Shao-Ming Yu

Ming-Huan Tsai

Chih-Yu Lai

Chun-Hsiang Fan

Chih-Hsiang Chang

Tsai-Fu Chen

Tsai-Fu Hsiao

Hongfa Luan

Sheng-Wen Yu

Chih-An Huang

Pei-Yi Lin

Hsiu-Chuan Chu

Wen-Feng Chueh

Chia-Shiung Tsai

Chung-Yi Yu

Yi-Wei Chen

Chun-Hung Lee

Hsin-Chih Chen

Chia-Wen Liang

Chao-Ching Hsieh

Jeffrey Junhao Xu

Chia-Chi Chung

Hsiao-Ling Lu

Wei-Chi Lin

Tung-Ti Yeh

Chao-Lon Yang

A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Wrap-around contact on FinFET

Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.

Inter-level connection for multi-layer structures

A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.

System for chemical mechanical polishing of Ge-based materials and devices

A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.

Method of forming the gate electrode of field effect transistor

A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.

A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.

Fin structure of FinFET

A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Self-aligned dual-metal silicide and germanide formation

Slurry composition for chemical mechanical polishing of GE-based materials and devices

A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.

Method of forming a semiconductor device

Growing community of inventors

Sinshih, Taiwan

Neng-Kuo Chen