Taiwan Semiconductor Manufacturing Comp. Ltd.

Neng-Jye Yang

Jian-Jou Lian

Li-Min Chen

Chia-Wei Wu

Kuo Bin Huang

Kuo-Bin Huang

Yao-Wen Hsu

Chii-Ping Chen

Hsiu-Wen Hsueh

Chun-Li Chou

Kuan-Lin Chen

Wan Hsuan Hsu

Ya-Ching Tseng

Ming-Hsi Yeh

Shun Wu Lin

Yu-Wen Wang

Jao Sheng Huang

Chung-Chi Ko

Liang-Guang Chen

Ya-Lien Lee

Chi-Ming Tsai

Fu-Ming Huang

Han-Hsin Kuo

Cai-Ling Wu

Nai-Chia Chen

An-Jiao Fu

Yen-Chiu Kuo

Yu-Li Cheng

Ya Tzu Chen

Ching-Hua Hsieh

Huang-Yi Huang

Szu-Ping Tung

Ming-Che Ku

Shih Min Chang

Chun-Hung Chao

Hsiao-Chieh Chou

Hao Yang

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

Self-aligned scheme for semiconductor device and method of forming the same

Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.

Diffusion barrier layer for conductive via to decrease contact resistance

Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

Surface modification layer for conductive feature formation

The present disclosure is at least directed to utilizing air curtain devices to form air curtains to separate and isolate areas in which respective workpieces are stored from a transfer compartment within a workpiece processing apparatus. The transfer compartment of the workpiece processing apparatus includes a robot configured to transfer or transport ones of the workpieces to and from these respective storage areas through the transfer compartment and to and from a tool compartment. A tool is present in the tool compartment for processing and refining the respective workpieces. Clean dry air (CDA) may be circulated through the respective storage areas. The air curtains formed by the air curtain devices and the circulation of CDA through the respective storage areas reduces the likelihood of the generation of defects, damages, and degradation of the workpieces when present within the workpiece processing apparatus.

Air curtain device and workpiece processing tool

An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Semiconductor devices and methods of manufacturing

A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Semiconductor device and method of manufacture

Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.

Method and structure of middle layer removal

Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.

An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

A middle layer removal method is provided. The method includes providing a substrate having a structure formed on the substrate, and forming a spacer layer on the structure. The method includes forming a mask layer over the spacer layer, the mask layer including a first layer, a second layer over the first layer, and a third layer over the second layer. The method also includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose a bottom surface of the second layer. The method further includes removing the second layer using a wet etchant.

A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

Chemical composition for tri-layer removal

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Hsinchu, Taiwan

Neng-Jye Yang