United Microelectronics Corp.

Neng-Hui Yang

Yu-Ren Wang

I-Cheng Hu

Chueh-Yang Liu

Chin-Cheng Chien

Yu-Ying Lin

Ming-Sheng Yang

Yu-Shu Lin

Shi-You Liu

Hsiang-Ying Wang

Ming-Shiou Hsieh

Rong-Sin Lin

Cheng-Yuan Tsai

Chun-Yao Yang

Hsin-Chang Wu

Yu-Kun Chen

Han-Ting Yen

Shui-Yen Lu

Tsai-Yu Wen

Ching-I Li

Tien-I Wu

Yu Shu Lin

Kuan Hsuan Ku

Chun Yao Yang

Yi-Wei Chen

Chun-Jen Chen

Ya-Lun Cheng

Chih-Chien Liu

Li-Wei Feng

Chun-Yi Lee

Shu-Yen Chan

Chien-Liang Lin

Kuang-Hsiu Chen

Chun-Wei Yu

YI-Fan Li

Ming-Hua Chang

Tien-Chen Chan

Yi-Liang Ye

Keng-Jen Lin

Sheng-Hsu Liu

Ted Ming-Lang Guo

Li-Chieh Hsu

Chun-Yu Chen

Hsu Ting

Yi-Fang Cheng

Chung-Min Tsai

Chieh-Lung Wu

Tsung-Tang Hsieh

Huan-Shun Lin

Yi-Chia Lee

Kuo Feng Huang

Chien-Mei Wang

Yu-Wen Fang

Wen-Hsun Lin

Chinh-Fu Lin

A method for fabricating semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a pad oxide layer on the substrate, wherein the pad oxide layer comprises a first thickness; performing an implantation process to inject germanium (Ge) into the substrate on the PMOS region; performing a first cleaning process to reduce the first thickness of the pad oxide layer on the PMOS region to a second thickness; performing an anneal process; and performing a second cleaning process to remove the pad oxide layer.

Method for fabricating semiconductor device

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.

Field-effect transistor

An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

Apparatus for semiconductor wafer treatment and semiconductor wafer treatment

A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Manufacturing method of semiconductor device

A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

Method for manufacturing fins

A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.

Field-effect transistor and method of making the same

An epitaxial structure of semiconductor device includes a substrate, a recess, a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer. The recess is formed in the substrate and disposed near a surface of the substrate, wherein the recess has a recess depth. The first epitaxial layer is disposed on surfaces of a sidewall and a bottom of the recess. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein the Ge concentration of the second epitaxial layer is greater than the Ge concentration of the first epitaxial layer. The third epitaxial layer is disposed on the surface of the second epitaxial layer, wherein the Ge concentration of the third epitaxial layer is greater than the Ge concentration of the second epitaxial layer, and the depth of the third epitaxial layer is about &#xbd; to about &#xbe; of the recess depth.

Epitaxial structure of semiconductor device and manufacturing method thereof

A method of fabricating an epitaxial layer includes providing a silicon substrate. A dielectric layer covers the silicon substrate. A recess is formed in the silicon substrate and the dielectric layer. A selective epitaxial growth process and a non-selective epitaxial growth process are performed in sequence to respectively form a first epitaxial layer and a second epitaxial layer. The first epitaxial layer does not cover the top surface of the dielectric layer. The recess is filled by the first epitaxial layer and the second epitaxial layer. Finally, the first epitaxial layer and the second epitaxial layer are planarized.

Method of fabricating epitaxial layer

Semiconductor device and manufacturing method thereof

The present invention provides a metal oxide semiconductor (MOS) device, including a substrate, a gate structure on the substrate and a source/drain region disposed in the substrate at one side of the gate structure and in at least a part of an epitaxial structure, wherein the epitaxial structure includes a first buffer layer, which is an un-doped buffer layer, including a bottom portion disposed on a bottom surface of the epitaxial structure and a sidewall portion disposed on a concave sidewall of the epitaxial structure, an epitaxial layer which is encompassed by the first buffer layer, and a semiconductor layer which is disposed between the first buffer layer and the epitaxial layer. The source/drain region is disposed in the epitaxial structure.

MOS device with epitaxial structure associated with source/drain region and method of forming the same

A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.

Method for manufacturing semiconductor device with epitaxial structure

A gate forming process includes the following steps. A gate dielectric layer is formed on a substrate. A barrier layer is formed on the gate dielectric layer. A silicon seed layer and a silicon layer are sequentially and directly formed on the barrier layer, wherein the silicon seed layer and the silicon layer are formed by different precursors.

Gate and gate forming process

A semiconductor device includes a substrate, a gate structure, a spacer, and a plurality of hyper-sigma (&#x3a3;) shaped epitaxial stressors. The substrate includes a first semiconductor material, and the hyper-&#x3a3; shaped epitaxial stressors include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The hyper-&#x3a3; shaped epitaxial stressors respectively include a first portion, a second portion and a neck physically connecting the first portion and the second portion. The first portion includes a pair of first tips pointing toward the gate structure in a cross-sectional view. The second portion includes a pair of second tips pointing toward the gate structure in the cross-sectional view. The neck includes a first slanted surface in the first portion and a second slanted surface in the second portion.

Semiconductor device with epitaxial structure and manufacturing method thereof

Growing community of inventors

Hsinchu, Taiwan

Neng-Hui Yang