Nxp B.v.

St-ericsson Sa

Integrated Device Technology, Inc.

St Wireless Sa

Nenad Pavlovic

Dominicus Martinus Wilhelmus Leenaerts

Lukas Frederik Tiemeijer

Jan Van Sinderen

Vladislav Dyachenko

Xin He

Manel Collados Asensio

Johannes Hubertus Antonius Brekelmans

Tarik Saric

Jozef Reinerus Maria Bergervoet

Edwin Van Der Heijden

Paulus T M Van Zeijl

Vojkan Vidojkovic

Frank Harald Erich Ho Chung Leong

Manel Collados

Chuang Lu

Reinier Hoogendoorn

Manuel Collados Asensio

Ketan Mistry

Hugo Veenstra

Dominicus M W Leenaerts

Ramon J Havens

A method of controlling a frequency-modulated oscillatorof a phase-locked loop circuitis described, wherein the oscillatorcomprises a bank of capacitors. The method comprises the steps of (i) switching a capacitorof the bank of capacitorsto change an output frequencyof an output signalof the oscillatorfrom a first frequencyto a second frequency, (ii) determining a frequency information associated with the capacitorand based on at least one of the first frequencyand the second frequency; and (iii) writing the frequency information to a look-up tablestored in a control unitof the oscillator. A corresponding frequency-modulated oscillatorand phase-locked loop circuitare also described.

Method of controlling a frequency-modulated oscillator of a phase-locked loop circuit

Embodiments of a method for operating a charge pump and a charge pump are disclosed. In an embodiment, a method for operating a charge pump involves during a first operating phase of the charge pump, setting a first current source of the charge pump according to a second current source of the charge pump, and, during a second operating phase of the charge pump that is subsequent to the first operating phase, providing current from the first current source to a load of the charge pump.

Charge pump and method for operating a charge pump

A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.

Digitally controlled oscillator

Embodiments of a clock synchronization unit of an All Digital Phase-Locked Loop (ADPLL), a successive approximation register (SAR) Time-to-Digital Converter (TDC) of an ADPLL and a method for clock synchronization in an ADPLL are disclosed. In one embodiment, a clock synchronization unit of an ADPLL includes a two-flop synchronizer, a phase frequency detector (PFD) connected to the two-flop synchronizer, and a synchronization control circuit configured to control the two-flop synchronizer and the PFD to perform clock synchronization between a reference clock input signal and a divided clock input signal and to control the two-flop synchronizer and the PFD to replace a performance of the clock synchronization between the reference clock input signal and the divided clock input signal with a PFD operation. Other embodiments are also described.

Clock synchronization in an ADPLL

A time to digital converter may include a synchronization block configured to output a voltage pulse with duration based on a time difference between a reference oscillating signal and an input oscillating signal; a charge pump arranged to receive the voltage pulse and to convert the voltage pulse into a current pulse; an integrator comprising an integrator capacitor, the integrator being configured to receive the current pulse and integrate the current pulse as a charge on the integrator capacitor, resulting in an integrator output voltage; and a successive approximation register configured to determine the integrator output voltage with respect to a reference voltage by adjusting the charge on the integrator capacitor so as to reduce the integrator output voltage to within a least significant bit (D0) of a reference voltage by successive approximation, and configured to output the determined integrator output voltage as a digital signal.

Time to digital converter and phase locked loop

A phase locked loop is disclosed having a frequency controlled oscillator, a feedback path, a time to digital converter and a memory. The frequency controlled oscillator comprises a first control input for varying the frequency of the output of the frequency controlled oscillator so as to track a reference frequency and a second control input for modulating the frequency of the output signal so as to produce a chirp. The feedback path is configured to provide an input signal to the time to digital converter, and comprises modulation cancelling module operable to remove the frequency modulation resulting from the second control input from the output signal. The memory stores second control input values that each correspond with a desired chirp frequency and which compensate for non-linearity in the response of the frequency controlled oscillator to the second control input. The phase locked loop is operable in a chirp mode, in which the second control input is produced by determining a value for the second control input corresponding with a desired chirp frequency based on the stored second control input values in the memory, and in which the phase locked loop is configured to determine the first control input based on the feedback path from which the modulation cancelling module has removed the frequency modulation resulting from the second control input.

A sigma delta receiver achieves increased stability and noise reduction. The sigma delta receiver includes a first integrator stage, an isolation stage, a second integrator stage, and a quantization stage. The first integrator stage receives an analog radio frequency (RF) signal from an antenna and generates an analog baseband signal based on the analog RF signal. The isolation stage is coupled to an output of the first integrator stage. The isolation stage receives the analog baseband signal from the first integrator stage and amplifies the analog baseband signal. The second integrator stage is coupled to an output of the isolation stage to receive the analog baseband signal. The second integrator stage further amplifies the analog baseband signal. The quantization stage converts the analog baseband signal to a digital signal, and outputs the digital signal.

Direct sigma-delta receiver

The invention relates to frequency conversion systems, in particular for use as up-converters or down-converters in radiofrequency (RF) receivers or transmitters, exemplary embodiments including a radiofrequency receiver including an RF signal input; a mixing module including a first plurality of IF amplifiers each connected to the RF signal input via a switch; a multi-phase local oscillator signal generator configured to provide a switching signal to each switch; and a summing module configured to receive output signals from each of the IF amplifiers and to provide a second plurality of output IF signals from a weighted sum of the IF amplifier output signals, wherein the second plurality is different to the first plurality.

Conversion system

An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.

Oscillator circuit

The present invention relates to a polar signal generator and method of deriving phase and amplitude components from in-phase (I) and quadrature-phase (Q) components of an input signal, wherein the I and Q components are generated at a first sampling frequency based on the input signal, and are then up-sampled in accordance with a predetermined first interpolation factor (N), to generate up-sampled I and Q components at a second sampling frequency higher than the first sampling frequency. The up-sampled I and Q components are converted into the phase and amplitude components, wherein the converting step is operated at the second sampling frequency. Moreover, the phase and amplitude components can be further up-sampled, optionally by different sampling frequencies, to a third and a fourth sampling frequency. Thereby, I-Q generation and cartesian-to-polar transformation can be performed at lower frequencies, which reduces power consumption.

Polar signal generator

The invention relates to a digital signal generator for providing one or more phases of a local oscillator signal for use in digital to analogue converters and harmonic rejection mixers. Embodiments disclosed include a local oscillator signal generator () for a mixer of a radiofrequency receiver, the signal generator () comprising a bit sequence generator () having a plurality of parallel output lines (), a digital signal generator () having a serial output line () and a plurality of input lines connected to respective output lines () of the bit sequence generator () and a clock signal input line (), wherein the digital signal generator () is configured to provide an output bit sequence on the serial output line () at a rate given by a clock signal provided on the clock signal input line () and a sequence given by a sequence of bits from the bit sequence generator () on the plurality of input lines ().

Digital signal generator

The present application relates to at least one digitally controlled oscillator and a data modulation device. More particularly, the digital polar transmitter comprises at least one digitally controlled oscillator configured to generate at least one frequency. The digital polar transmitter comprises a data modulation device, wherein the data modulation device comprises at least one data input terminal, at least one output terminal, and at least one frequency input terminal, wherein the output terminal is connected to the digitally controlled oscillator. The digital polar transmitter comprises a phase measuring device configured to measure phase information from the output signal of the data modulation device for every frequency sample. The digital polar transmitter comprises a phase error detecting device configured to detect a phase error at least depending on the measured phase information, wherein the phase error detecting device is configured to apply the detected phase error to the output signal of the data modulation device.

Polar transmitter

Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.

Circuit with a time to digital converter and phase measuring method

A digital phase locked loop () configured to receive a reference clock signal () and a channel control word (), and to generate an output clock signal (). The digital phase locked loop comprising an adjustable delay component () configured to: receive the reference clock signal (), apply a time delay to the reference clock signal () in accordance with a time delay control signal (); and provide a delayed reference clock signal (). The digital phase locked loop further comprising a timing component () configured to process the delayed reference clock signal () and the output clock signal (), and generate a first control signal () representative of the phase of the output clock signal (); a reference accumulator () configured to receive the channel command word () and generate: a second control signal () representative of the phase of an intended output clock signal; and the time delay control signal () such that the delayed reference clock signal () is delayed by a period of time representative of a first portion of the phase of the intended output clock signal. The digital phase locked loop also comprising a controller () configured to process the first and second control signals (), and generate a DCO control signal () for setting the frequency of a digitally controlled oscillator () in accordance with the first and second control signals (); and a digitally controlled oscillator () configured to generate the output clock signal () in accordance with the DCO control signal ().

Digital phase locked loop

An output stage () for a digital RF transmitter is provided. The output stage comprises: an input adapted to receive an input signal (RFin, b-b) to be transmitted; a plurality N of power amplification sections (S, S, S, S); and an output (A, B) providing an output voltage signal. Each of the N power amplification sections (S, S, S, S) is arranged to receive the input signal (RFin, b-b) and comprises a transformer (T, T, T, T) adapted to provide a respective output signal. Each transformer comprises a primary stage and a secondary stage; the secondary stages of the transformers (T, T, T, T) of the N power amplification sections (S, S, S, S) are combined such that a combined output voltage signal of the output stage is provided. The N power amplification sections (S, S, S, S) are adapted such that the input signal (RFin, b-b) is latched by clock signals (clock, clock, clock, clock) comprising different phases.

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Eindhoven, Netherlands

Nenad Pavlovic