International Business Machines Corporation

Nelson S Xu

Lisa Cranton Heller

Kenneth Anthony Lauricella

Robert Michael Dinkjian

Thomas W Seigendall

Steven R Kordus

Robert A Skaggs

James A O'Connor

Russell S Cook

Harold J Broker

A data processor processes data strings from memory where the data strings do not begin or end at a memory boundary. A string is defined in memory by a starting address, a byte count defining the total number of bytes in the string, and a byte offset defining the position of the first byte in the starting address location. The processor stores the byte count and decrements the byte count as each multi-byte word is processed. A byte count mask circuit generates a byte count mask which has all 1s for each byte count greater than the number of bytes per memory word. When the number of bytes remaining to be processed is below the number of bytes in a memory word, the byte count mask generates 1s only for the positions corresponding to the positions of bytes of the string in the last memory word. An offset register stores the offset defining the position of the first byte in the first memory word of the string. The offset is used to shift the byte count mask by a number of positions corresponding to the position of the first byte of the string and inserts 0s in the byte count mask for positions not belonging to the string. A byte-by-byte comparator determines string end conditions and provides an output word with a significant bit indication for each byte for which an end condition has been detected. The output of the byte-by-byte comparator is combined with the shifted byte count mask, and the result is decoded by means of a prioritized decoder which generates a string write mask.

Hardware implementation of string instructions

Method of processing data strings

Processor for processing data string by byte-by-byte

A high speed digital multiplier utilizes a variation in known shift-and-add algorithms. Each cycle, a single digit of the multiplier and the entire multiplicand are processed to form a 'partial product' that is added to the result of the next cycle. The end result is a two part product, the high order product being generated by a carry-propagate adder, and the low order product being generated by a 'spill adder' that produces one digit each cycle. Inputs of a carry-propagate adder are fed directly from outputs of a carry-save adder rather than running sum and carry registers. With a multiplier digit of 16-bits, a fixed point halfword multiply requires one execution cycle, a fixed point fullword multiply requires two execution cycles, and a floating point long multiply requires four execution cycles with additional overhead if pre- or post-normalization is required.

High speed multiplier

Growing community of inventors

Hyde Park, NY, United States of America

Nelson S Xu