Intel Corporation

Neil Schaper

Joydeep Ray

Altug Koker

Gilbert A Neiger

Rajesh M Sankaran

Blaise B Fanning

Raj K Ramanujan

David M Puffer

Yen-Cheng Liu

Joseph Nuzman

Vladimir M Pentkovski

Aditya Sreenivas

Bryan R White

Larisa Novakovsky

Deep K Buch

Todd M Witter

Marc D Torrant

David Zhao

Zhenjun Hu

A processing device comprises an instruction execution unit, a memory agent and pinning logic to pin memory pages in a multi-level memory system upon request by the memory agent. The pinning logic includes an agent interface module to receive, from the memory agent, a pin request indicating a first memory page in the multi-level memory system, the multi-level memory system comprising a near memory and a far memory. The pinning logic further includes a memory interface module to retrieve the first memory page from the far memory and write the first memory page to the near memory. In addition, the pinning logic also includes a descriptor table management module to mark the first memory page as pinned in the near memory, wherein marking the first memory page as pinned comprises setting a pinning bit corresponding to the first memory page in a cache descriptor table and to prevent the first memory page from being evicted from the near memory when the first memory page is marked as pinned.

Isochronous agent data pinning in a multi-level memory system

An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.

Method and apparatus for cache line write back operation

A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0&#x3c;n&#x3c;=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.

Multiprocessor-scalable streaming data server arrangement

Growing community of inventors

Folsom, CA, United States of America

Neil Schaper