Plessey Semiconductors Limited

Neil S Hastie

Richard Albon

David A Williams

In a contents addressable memory for a fully associative cache memory in which address bit values in respect of data to be retrieved from cache are applied to the bit lines of respective columns of cells for comparison with the bit values held by the cells, a match in any one cell is arranged to forward bias a match line device in that cell, the match line devices of a row being connected in cascade, so that if a match is obtained along a row a current path is provided along the row to a respective current sensing circuit to indicate the match.

Content addressable memory having match line transistors connected in

A programmable logic cell suitable for use in a programmable gate array and able to produce any logical function of two inputs, operate as a 2 to 1 multiplexor or a data latch is formed by four multiplexors, five inverters and an OR gate to provide a very fast programmable logic cell.

Programmable multiplexer logic cell

A programmable logic cell has two inputs and six outputs, each output being a different logical function of the inputs. Each output is generated by a pair of NMOS transistors, one transistor of each pair having its gate connected to one of the inputs and the other transistor of each pair having its gate connected to the inverse of the same input.

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Plymouth, United Kingdom

Neil S Hastie