Stmicroelectronics Gmbh

Sgs-thomson Microelectronics Limited

Other

Neil Richards

Gajinder Singh Panesar

Peter William Thompson

John A Carey

Marcello Coppola

Robert John Simpson

Pascal Moniot

Pierre Dumas

David Mouen Makoua

Peter Thompson

Thierry Grenot

Vincent Cottignies

A data reception unit for receiving a plurality of data streams over a data channel, the data streams being received as amounts of data and each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream, the data reception unit comprising: a data stream memory comprising a plurality of data stream storage areas, each for storing data from a respective one of a set of the data streams, and an escape buffer; a first storage information memory for holding first storage information for facilitating storage in the respective data stream storage area of data from the set of the data streams; and a data storage controller for, for each received amount of data, receiving the identity portion of the amount of data and performing a storage operation comprising: accessing the first storage information memory; and if the first storage information memory holds first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the data stream storage area corresponding to that data stream; and if the first storage information memory does not hold first storage information for the data stream identified by the identity portion, storing the data portion of the amount of data in the escape buffer; and a processing unit connected to the escape buffer for performing an assembly operation comprising executing steps to assemble the information stored in the escape buffer into respective data streams.

Data transmission apparatus for transmitting ATM data streams

A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Data transfer

Data reception apparatus for receiving ATM data streams

A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Reception of multiple data messages over a transmission medium with conversion into suitable form

A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas, and a buffer; a first storage information memory for holding first storage information a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.

Data stream transfer apparatus for receiving a data stream of data cells at variable time intervals and transmitting data frames at predetermined time intervals, including a receiving apparatus, a buffer memory, a data transfer interface, a central processing unit (CPU), and a memory access unit. The receiving apparatus receives the data cells and stores them in the buffer memory. The data transfer interface transfers data frames out of the apparatus at the predetermined time intervals and generates an indication that the data frame has been transferred. The memory access unit receives data defining a location of a data frame in the buffer memory, accesses the buffer memory to retrieve that data frame and transmits that data frame to the data transfer interface. The CPU, upon receiving the indication, determines a time for transfer of a subsequent data frame, and upon reaching that time, transmits to the memory access unit the location of the subsequent frame in the buffer memory.

Data stream transfer apparatus for receiving a data stream and transmitting data frames at predetermined intervals

A data reception unit for receiving a plurality of data streams over a data chanel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas and a reserve buffer, a first storage information memory for holding first storage information, a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation-based on the identity portion.

Device for segmentation and transmission of messages stored as blocks of variable length

An ATM routing switch has a buffer circuit for holding cells located on queues at output ports, the buffer having a first reserve buffer capacity for cells of a first type requiring integrity of cell transmission and a first designation for use in determining a permitted path through the network, a second reserve buffer capacity for cells of the first type having a second designation for use in determining a different permitted path in the network and a third reserve buffer capacity for cells of a second type accepting some loss of cells in transmission, flow control circuitry operating to limit input of cells of either the first or second type if predetermined thresholds for the first, second or third buffer capacities are reached.

ATM switch for routing different cell types

Apparatus for re-assembling information cells of messages, comprising a message memory, a message data memory, a location memory, and loading apparatus. The message memory stores each message in blocks that can be different lengths. The message data memory stores, for each message, message data defining a location in message memory, a position in the block, and a length of the block that is to receive the cells of the message. The location memory stores, for each message, an indication of the location of the message data. The loading apparatus receives the cells, and for each cell, accesses location memory to determine the location of message data, stores the cell in the message memory at the indicated location, increments the message data defining the location and the position, and compares the incremented position with the stored length of the block to determine whether the end of the block has been reached.

An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.

Congestion avoidance in an ATM switch

An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

ATM switch

An ATM routing switch has a plurality of input and output ports and a buffer for holding a plurality of ATM cells, the cells being held in the buffer as a plurality of queues (F0-F7), each formed as a chained list of addresses with front and back pointers identifying ends of each queue.

Cell queue formation in an ATM switch

A network of ATM routing switches transmits digital signal cells of a first type requiring integrity of transmission and a second type accepting some loss in transmission, each switch has buffer circuitry. a plurality of output ports each having a plurality of queues of cells awaiting output, each output port having control circuitry to provide in an output frame control bits indicating the type of cell, a path identifier and the existence of flow congestion at the routing switch which it outputting the frame, thereby inhibiting transmission of further frames to that location until a frame is received from that location indicating that the congestion is cleared.

ATM switch flow control

An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.

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East Brent, United Kingdom

Neil Richards