Cypress Semiconductor Corporation

Neil P Raftery

Jonathan F Churchill

Cathal G Phelan

Ashish Pancholy

Mark A Finn

Jeyakumar Shanmugam

Thomas M Surrette

Colin J Hendry

James W Lutley

Kenneth A Maher

Mathew R Arcoleo

An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii), a don't care state.

Wired address compare circuit and method

An apparatus including a first circuit and a second circuit. The first circuit may be configured to generate one or more enable signals in response to a first control signal and a clock signal. The second circuit may be configured to generate an output signal in response to the one or more enable signals and the clock signal. The first circuit is configured to sample a frequency of the clock signal.

Circuit and method for frequency generator control

A memory device includes an address pipeline configured to receive a write address at a first time and to provide the write address to a memory array at a second time, corresponding to a time when write data associated with the write address is available to be written to the array. The address pipeline may include a series of registers arranged to receive the write address and to provide the write address to the memory array. In addition, the memory device may include a comparator coupled to the address pipeline. The comparator is configured to compare the write address to another address (e.g., a read address) received at the memory device. A bypass path to the array may be provided for read addresses received at the memory device. A data pipeline is configured to receive data destined for the memory device and to provide the data to the memory array. The data pipeline may include a data bypass path which does not include the memory array.

Circuit architecture and method of writing data to a memory

An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.

A circuit for delaying a signal. The circuit includes a scan register, a logic circuit, and a programmable delay circuit. The scan register stores scan data and the logic circuit selectively decodes the scan data. The programmable delay circuit is coupled to the logic circuit and delays a signal a programmable amount of time in response to the decoded scan data.

Scan path circuitry including a programmable delay circuit

A circuit for generating a pulse including a scan register having a first scan bit; first logic device receiving a first signal and generating a second signal; and a programmable delay circuit coupled to the scan register and the first logic device. The programmable delay circuit receives the second signal and generates a delayed second signal after a programmable period of time. The programmable period of time is determined by the first scan bit. The circuit also includes a logic circuit that recevies the second signal and the delayed second signal. The logic circuiit outputs the pulse having a pulse width proportional to the programmable period of time.

Scan path circuitry for programming a variable clock pulse width

An integrated circuit including a first input for receiving a scan enable control signal and a second input for receiving a test mode control signal. The integrated circuit also includes a programmable scan circuit coupled to the first input and the second input. The programmable scan circuit configures the integrated device to operate in a default mode, a scan mode, or a test mode in response to the scan enable and test mode control signals.

Test mode features for synchronous pipelined memories

A circuit including a register coupled to a control circuit. The register has a synchronous mode of operation and an asynchronous mode of operation. The a control circuit controls whether the register operates in the synchronous mode or the asynchronous mode. The circuit may further include a scan register having scan data. The control circuit may cause the register to operate in the synchronous or asynchronous mode in response to the scan data.

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Guildford, United Kingdom

Neil P Raftery