3com Corporation

Hewlett-packard Development Company, L.p.

3com Technologies

Neil O Fanning

Eugene O'Neill

Joseph N Butler

Mark A Hughes

Kevin Jennings

Una Quinlan

Sorcha O'Callaghan

Con David Cremin

J Noel Butler

A network switch includes a look-up engine for obtaining associated data in response to a header portion of a packet and an interlinked network processor such as a RISC for performing a processing function on the header portion or the associated data. Both look-up engine and the network processor may modify a destination port bitmask. The network processor may implement additional packet header processing required for replication or server load balancing.

Network switch with mutually coupled look-up engine and network processor

An application specific integrated circuit includes a clock recovery circuit which recovers from an input signal a repetitive sequence of data values wherein no two consecutive values are the same and a recovered clock. An address generator responds to the recovered clock to cause storage of the data values in said memory in a set of locations having addresses generated by the address generator, so that the address generated by the generator increments in response to a repetitive transition in the recovered clock. The existence of a clock glitch is found by reading the data values from the set of locations to determine whether any two consecutive locations contain the same data value.

On-chip detection of clock gitches by examination of consecutive data

A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.

High speed parallel bit error rate tester

A plurality of serial data streams are transmitted on a corresponding plurality of lines at a common frequency in equal groups of symbols. A framing signal composed of groups of symbols corresponding in number to groups of data symbols is transmitted on an additional control line. Each group of symbols in the framing signal includes a majority of symbols capable of representing a first plurality of code words and a second plurality, substantially less than the first plurality, of valid code words, and a minority of symbols which constitute parity check symbols. Each of the valid code words consists of a first sub-group of similar symbols and a second plurality of similar symbols. For some of the valid code words the symbols in the first sub-group are similar to the symbols in the second sub-group. For other valid code words the symbols in the first sub-group are different from the symbols in the second sub-group. The valid code words correspond to groups which represent (a) start of a data packet or block; (b) data/(c) a gap between groups of data; and (d) an idle state. The sequence of groups in the framing signal is monitored by means of a state machine.

Framing codes for high-speed parallel data buses

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Kilworth, Ireland

Neil O Fanning