International Business Machines Corporation

Hitachi Global Storage Technologies Netherlands B.v.

Hgst Netherlands, B.v.

Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Hitachi Global Storage Technologies

Hitachi Global Technologies Netherlands B.v.

Neil Leslie Robertson

Jordan Asher Katine

Patrick Braganca

Yang Li

Mao-Min Chen

Barry C Stipe

Richard Hsiao

Hamid Balamane

Edward Hin Pong Lee

Albert John Wallash

Hugo Alberto Santini

Chie Ching Poon

Thomas Edward Dinan, Jr

Quang Le

Zvonimir Z Bandic

Neil Smith

Luiz M Franca-Neto

Michael Grobis

Timothy Scott Hughbanks

Jeffery Robinson Childress

Steven H Voldman

Kochan Ju

Glen A Garfunkel

Robert Fontana

Haiwen Xi

Jeffrey Scott Lille

Jeffrey Childress

Aron Pentek

Gerardo Bertero

Andrew Ching Tam

Surya Narayan Pattanaik

Jui-lung Li

Meng Ding

Qingbo Wang

Mac D Apodaca

Thomas Dudley Boone, Jr

James Lamar Nix

Michael Nicolas Albert Tran

Christian Rene Bonhote

Zhaoqiang Bai

Po-Kang Wang

Vladimir Nikitin

Daniele Mauri

Hemantha Kumar Wickramasinghe

Ward M Parkinson

Ching Hwa Tsang

Thomas Young Chang

Petrus Antonius Van Der Heijden

Timothy Carl Strand

Douglas Johnson Werner

Patrick Rush Webb

Lei Wan

Mason Lamar Williams

Scott Arthur MacDonald

Amanda Baer

Michael R Feldbaum

Ian Robson McFadyen

Prakash Kasiraj

Goran Mihajlovic

Samuel Wonder Yuan

Clinton David Snyder

Matteo Staffaroni

Vijay P S Rawat

Son Van Nguyen

Hendrik F Hamann

Christopher John Petti

Toshiki Hirano

Erhard Theodor Schreck

Cherngye Hwang

Ming Jiang

Kuok San Ho

Yves Corfield Martin

Tsann Lin

Matthew Joseph Carey

Murali Ramasubramanian

Yimin Hsu

Hugo Alberto Emilio Santini

Fu-Ying Huang

A David Erpelding

Paul Phong Nguyen

Jan-Ulrich Thiele

Howard Gordon Zolla

Sue Siyang Zhang

Edward Kihyen Lee

Abhijit Bandyopadhyay

Christopher H Bajorek

Huey-Ming Tzeng

David Eugene Heim

Michael J Armstrong

John C Read

Young-Suk Choi

Linden James Crawforth

Joseph Francis Smyth

Samuel Weisan Yuan

Vijay Prakash Singh Rawat

Peter Beverley Phipps

Samuel Wei-san Yuan

Kanaiyalal Patel

Petrus Antonius VanDerHeijden

Hin P Lee

In a memory array with a cross-point structure, at each cross-point junction a programmable resistive memory element, such as an MRAM memory cell, is connected in series with a threshold switching selector, such as an ovonic threshold switch. The threshold switching selector switches to a conducting state when a voltage above a threshold voltage is applied. When powered down for extended periods, the threshold voltage can drift upward. If the drift is excessive, this can make the memory cell difficult to access and can disturb stored data values when accessed. Techniques are presented to determine whether excessive voltage threshold drift may have occurred, including a read based test and a time based test.

Power off recovery in cross-point memory with threshold switching selectors

A spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) device includes a SOT MRAM cell containing a first two terminal selector element, a nonmagnetic metallic assist plate, and a magnetic tunnel junction located between the first two terminal selector element and the nonmagnetic metallic assist plate, and a circuit selection element selected from a transistor or a second two terminal selector element electrically connected to the nonmagnetic metallic assist plate of the SOT MRAM cell.

Method of making magnetoresistive memory cell over a selector pillar

Spin-orbit-torque magnetoresistive memory cell with integrated selector elements and method of making the same

A two-step SET pulse may be applied to a phase change material of a phase change memory cell in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

Set/reset methods for crystallization improvement in phase change memories

A phase change memory device includes a phase change material portion located between a first electrode and a second electrode, and a crystallization template material portion located between the first electrode and the second electrode in contact with the phase change material portion. The crystallization template material portion and the phase change material portion belong to a same crystal system and have matching lattice spacing, or the crystallization template material portion and the phase change material portion do not belong to the same crystal system, but have a matching translational symmetry along at least one paired lattice plane with a matching lattice spacing.

Phase change memory device with crystallization template and method of making the same

Systems and methods for improving the crystallization of a phase change material of a phase change memory cell are described. A two-step SET pulse may be applied to the phase change material in which a first lower SET pulse is applied to make the phase change material dwell at 600K to incubate nuclei near the maximum nucleation rate and then a second higher SET pulse is immediately applied to make the phase change material dwell at 720K to maximize crystal growth. Moreover, the slope of the falling edge of a RESET pulse applied prior to the two-step SET pulse may be adjusted to increase the number of nuclei (e.g., formed with a steeper falling edge) to increase SET efficiency at the expense of a more stable amorphous phase (e.g., formed with a less steep falling edge) that improves data retention.

A system according to one embodiment includes a pinned layer; a spacer layer above the pinned layer; a free layer above the spacer layer; a heating device, for heating the free layer to induce a paramagnetic thermal instability in the free layer whereby a magnetization of the free layer randomly switches between different detectable magnetic states upon heating thereof; and a magnetoresistance detection circuit for detecting an instantaneous magnetic state of the free layer.

Random number generator by superparamagnetism

A memory cell includes a VCMA magnetoelectric memory element and a two-terminal selector element connected in series to the magnetoelectric memory element.

Magnetoelectric random access memory array and methods of operating the same

An MRAM memory cell is proposed that is based on spin accumulation torque. One embodiment includes a magnetic tunnel junction, a spin accumulation layer connected to the magnetic tunnel junction and a polarization layer connected to the spin accumulation layer. The polarization layer and the spin accumulation layer use spin accumulation to provide a spin accumulation torque on the free magnetic layer of the magnetic tunnel junction to change direction of magnetization of the free magnetic layer.

Spin accumulation torque MRAM

A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M, and a second conductor Mand a programmable area using unpatterned programmable magnetic media. At least one of the conductors M, Mis formed of a magnetic material, and the conductor Mis more conductive than conductor M. Steering of current is provided for programming the magnetic memory cell.

Implementing enhanced magnetic memory cell

Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A plurality of read lines are in a read line layer, and a plurality of write lines are in a write line layer. A plurality of spin accumulation lines are in a spin accumulation line layer disposed between a read line layer and a write line layer. Spin accumulation lines may horizontally cross read lines and write lines. A plurality of vertical magnetoresistive random access memory (MRAM) cells may include polarizers and magnetic tunnel junctions. A vertical MRAM cell may include a polarizer coupled between a spin accumulation line and a write line. A vertical MRAM cell may further include a magnetic tunnel junction coupled between a spin accumulation line and a read line, such that the magnetic tunnel junction and the polarizer are vertically aligned.

Cross-point spin accumulation torque MRAM

A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Implementing magnetic memory integration with CMOS driving circuits

A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M, and a second conductor M, the second conductor Msurrounded by the first conductor Mand a programmable area using unpatterned programmable magnetic media. At least one of the conductors M, Mis formed of a magnetic material, and the conductor Mis more conductive than conductor M. An oxide barrier extends between the first conductor Mand a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Implementing magnetic memory pillar design

Growing community of inventors

Campbell, CA, United States of America

Neil Leslie Robertson