Prime Computer Inc.

Neil J Johnson

Brian K Langendorf

Robert F Beckwith

Suren Irukulla

Nihar Mohapatra

Steven Schwartz

A pipelined central processor capable of executing both single-cycle instructions and multicycle instructions is provided. An instruction fetch stage of the processor includes an instruction cache memory and a prediction cache memory that are commonly addressed by a program counter register. The instruction cache memory stores instructions of a program being executed and microinstructions of a multicycle instruction interpreter. The prediction cache memory stores interpreter call predictions and interpreter entry addresses at the addresses of the multicycle intructions. When a call prediction occurs, the entry address of the instruction interpreter is loaded into the program counter register on the processing cycle immediately following the call prediction, and a return address is pushed onto a stack. The microinstructions of the interpreter are fetched sequentially from the instruction cache memory. When the interpreter is completed, the prediction cache memory makes a return prediction. The return address is transferred from the stack to the program counter register on the processing cycle immediately following the return prediction, and normal program flow is resumed. The prediction cache memory also stores branch instruction predictions and branch target addresses.

High-performance pipelined central processor for predicting the

A branch cache system for use with a pipelined processor having overlapping parcel prefetch and execution stages. The system includes a plurality of memory sets for storing a plurality of indexed sets of predicted branch addresses, and control circuitry which determines whether there is stored in one of the memory sets a predicted branch address which corresponds to a branch instruction fetched by the prefetch stage. The execution stage is commanded, responsive to detection of a predicted branch address corresponding to that branch instruction, to execute the branch instruction to the predicted branch address. Alternatively, the system includes one or more memory sets for storing predicted branch addresses and corresponding alignment values which represent whether the boundary of a prefetched branch instruction, which is prefetched as one or more parcels, aligns with the fixed boundary of the one or more parcels containing that instruction. The execution stage is commanded to disregard the prefetched parcel containing a portion of the prefetched branch instruction if the alignment value corresponding to the predicted branch address for that prefetched instruction indicates that the boundary for the prefetched instruction does not align with the boundary of the prefetched parcel.

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Burlington, MA, United States of America

Neil J Johnson