Synopsys, Inc.

Elliptic Technologies Inc.

Elliptic Semiconductor Inc.

Other

Mosaid Technologies Corporation

Neil Hamilton

Michael Andrew Borza

Michael Bowler

Scott Andrew Hamilton

Andrew Alexander Elias

Michael James Lewis

Arthur John Low

François Bourdon

A A Jithra Adikari

Neil Leckett

Hafid Zaabab

A method is disclosed for providing first data and a first secret key to a cipher processor for ciphering. The first data is ciphered in accordance with a first cipher process and the first secret key to provide output data. Before ciphering of the first data, extra data is inserted within the cipher processor for ciphering in accordance with at least a portion of said first cipher process. The extra data is inserted within a sequence of cipher processor operations for obfuscating the output data.

System and method for cryptographic processing in a time window

A method for ciphering protected content communicated between a first device and a plurality of devices over a plurality of channels comprises performing authentication between the first device and each of the plurality of devices to create two or more shared key and initialization vector pairs allowing the ciphering of the protected content; generating a key stream for each of the channels based on a selected one of the two or more of shared key and initialization vector pairs; maintaining a buffer for each channel, each of the buffer containing the key stream generated for the corresponding channel; and ciphering data incoming on a selected channel using the selected key stream from the buffer corresponding to the selected channel.

Multiport content encryption engine

A system for reseeding a pseudo random number generator to generate pseudo random numbers includes a true random number generator generating a true random number, a storage device storing the generated true random number, a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed, and a controller coupled to the true random number generator and the pseudo random number generator to (1) generate a new true random number concurrently with the operation of the pseudo random number generator, and storing the new true random number, and (2) reseed the pseudo random number generator with the new true random number.

Automatic control system and method for a true random number generator

A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations.

Memory data transfer method and system

A processor is disclosed for ciphering of first data. The processor includes a key store and a first data store. In use the processor for ciphering the first data in accordance with a first cipher process and a first secret key to provide output data, during ciphering of the first data inserting within the cipher processor other data for ciphering in accordance with at least a portion of the first cipher process, the other data inserted within a sequence of cipher processor operations and scheduled for obfuscating the output data.

System and method for multichannel cryptographic processing

There is disclosed a cache memory controller for storing cache data within a cache, the cache data comprising an unsecured version data to corresponding secured first data.

Secured memory system and method therefor

A method of implementing large number multiplication and exponentiation is provided upon a general purpose microprocessor. These large number multiplication and exponentiation processes being common to cryptography standards such as RSA and AES that typically employ numbers with 512-bits, 1024-bits, and 2048-bits. According to the invention the method establishes the size of the large number processes according to value stored within a control register, this control register and other registers storing data are configured according to this value and accessed as N-bit registers (i.e. as 1024-bit registers for 1024-bit encryption. Additionally, the multiplication and exponentiation processes are handled according to the size of an arithmetic primitive, which is established according to the hardware configuration upon which the process is operating. As such the invention allows for an encryption process to adjust both to the configuration of the host microprocessor and supporting hardware/firmware and dynamically according to degree of security determined from the value stored within the control register.

Flexible architecture for processing of large numbers and method therefor

A random number generator includes a first circuit producing a random sequence of values, the first circuit having an adjustable input that changes the entropy of the random sequence of numbers; a second circuit receiving the random sequence of values from the first circuit and producing an output indicative of the degree of entropy of the random sequence of values, and a third circuit that adjusts the adjustable input of the first circuit in response to the output of the second circuit.

System and method for dynamic tuning feedback control for random number generator

A method is disclosed for intermixing a first stream of data and a second stream of data. An associated first secret key is expanded to form a first associated expanded secret key. An associated second secret key is expanded to form a second associated expanded secret key. The first stream of data and the second stream of data are intermixed to form a combined stream of data, which is ciphered. The combined stream of data is de-multiplexed after ciphering thereof and provided at an output port.

Cryptographic sequencing system and method

An architecture for use in packet processing and supporting compatibility with current BSD implementations for packet processing is proposed wherein two MBUF formats are supported. A first format includes a header portion and a data portion for storing data therein. A second format includes a header portion but is absent a data portion and is for addressing data stored within a cluster and external to the MBUF itself.

Packet memory processing system having memory buffers with different architectures and method therefor

A method and apparatus are disclosed for prefragmenting or presegmenting data. A data protocol type and length are provided. Based on the type and length, a linked list memory buffer structure is determined. Locations within the memory buffer structure for storage of data therein is also determined allowing for sufficient unused memory therein to support one of a fragmentation operation and a segmentation operation subsequent to memory allocation. As such, further memory allocation during a fragmentation operation or a segmentation operation is obviated. The determined memory buffer structure is then allocated.

Growing community of inventors

Kanata, Canada

Neil Hamilton