Xilinx, Inc.

Other

Xilinix, Inc.

A.t.e. Solutions, Inc.

Neil G Jacobson

Sanjay Srivastava

Bin Dai

Sungnien Jerry Mao

Emigdio M Flores, Jr

Rosa M Y Chow

Pushpasheel Tawade

Derek R Curd

Matthew T Murphy

Kameswara K Rao

David Chiang

Napoleon W Lee

Sholeh Diba

Wei-Yi Ku

John D Corbett

David P Schultz

Robert O Conn

Tim Tuan

Wayne Edward Wennekamp

Tak Ming Mak

Anthony J Collins

James A Walstrum, Jr

Brian D Erickson

Edward S McGettigan

Bradley K Fross

Randal M Kuramoto

Kang Wu

Louis Yehuda Ungar

Bernardo A Elayda, Iii

Anthony S Maraldo

Sanja Srivastava

David E Schweigler

Emigdio M Flores Jr

A dynamically reconfigurable interface for an automatic test equipment is disclosed where one or more synthetic instruments transmit the high speed signals as well as receive the high speed signals from a device under test so that testing can be performed at speeds higher than the ATE was originally designed to accommodate. Synthetic instruments are implemented on a field programmable gate array (FPGA) that operate at higher speeds than COTS instruments and can reach the frequencies that high speed I/O buses use. SIs can be created by configuring the FPGA, with different configurations creating different SIs. A single FPGA can house a number of SIs.

Systems and methods for dynamically reconfiguring automatic test equipment

A computer-implemented method of reducing susceptibility of a circuit design to single event upsets can include determining a susceptibility level of the circuit design to single event upsets, comparing the susceptibility level with a target susceptibility, and selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility. The circuit design including the mitigated region can be output.

Reducing susceptibility of circuit designs to single event upsets

A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

Identifying bitstream load issues in an integrated circuit

A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.

Determining a cycle basis of a directed graph

A computer-implemented method of verifying electrical isolation of portions of a circuit design for a programmable integrated circuit (IC) can include translating a circuit design into a circuit design bitstream specifying a plurality of regions, wherein the regions are to be isolated from one another. Routing resources of the programmable IC that are not used by the circuit design can be identified. A fence bitstream can be generated that specifies the unused routing resources. The circuit design bitstream can be compared with the fence bitstream. An indication of whether the plurality of regions of the programmable IC are isolated can be output according to the comparison.

Verifying design isolation using bitstreams

Methods and apparatus are disclosed for identifying a system. In various embodiments, values of identification codes are read from each of a plurality of electronic devices of the system. The values of the identification codes are used to generate a system identifier value.

Identification of multi-device systems

A memory coupled to a programmable logic device (PLD) is configured through the PLD's JTAG port. A soft core loaded into the PLD connects to the JTAG port and memory. An external programming host device connects to the JTAG port, sends instructions and data to and receives data from the memory via the JTAG port and soft core. A synchronization JTAG instruction is loaded, and a Shift Data state of the JTAG port state machine is used. The programming host device and soft core are synchronized, and a memory chip select is asserted. A memory instruction, such as READ, WRITE or ERASE is loaded into the memory. An RTI state of the state machine is used to wait for instruction completion and the chip select is deasserted. Another instruction is processed starting with using the Shift Data state. Alternatively, a PLD Shift Data Register is used in conjunction with the soft core.

JTAG to SPI PROM conduit

Methods and systems are provided for determining a total length of instruction registers. A data shift of a scan chain determines whether each device in the scan chain is an identified device. An overall length of the instruction registers of the devices is determined from an instruction shift. An actual position is determined for an identified device between each pair of sub-sequences of unidentified devices. An instruction shift of the scan chain attempts to set the respective instruction register of the identified device using one or more trial positions. If a data shift of the scan chain obtains the recognized value of the respective identification register of the identified device for one of the trial positions, then this trial position is the actual position within the overall length. The total length is determined for the instruction registers of the unidentified devices in each sub-sequence of the unidentified devices.

Determining a length of the instruction register of an unidentified device on a scan chain

A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Method and mechanism for controlling power consumption of an integrated circuit

Methods and apparatus are disclosed for managing configuration data for a system. In various embodiments, a chain description data set is generated to specify an order in a configuration chain of configurable devices in the system and identify configuration data sets associated with the configurable devices. A system identifier value is generated and associated with the chain description data set. An archive is generated including the configuration data sets, chain description data set, and system identifier value.

Management of configuration data by generating a chain description data set that specifies an order of configuration chain for multi-device systems

Provision of configuration access to a programmable device such as a programmable logic device (PLD) via a boundary-scannable devices. In one embodiment a configuration controller is arranged to transfer configuration data that specify configuration access for the PLD. A scan controller is coupled to the configuration controller and arranged to generate boundary-scan signals responsive to configuration data from the configuration controller. At least one boundary-scannable device has a plurality of boundary-scan pins coupled to the scan controller, and a PLD is coupled to the boundary-scannable device.

Configuration access from a boundary-scannable device

Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

Monitoring the state vector of a test access port

A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.

System and method for overcoming download cable bottlenecks during programming of integrated circuit devices

Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

Transmitting configuration data to a target programmable device after updating an intermediate programmable device

A bitstream having a plurality of data sets is provided to an integrated circuit device such as an FPGA having test circuitry capable of routing data to the device's internal resources, with each data set including configuration information and a trigger signal. Successive data sets of the bitstream are sequentially processed by the test circuitry in response to the trigger signals to sequentially initialize the device's resources to various states. For some embodiments, each data set includes configuration data to configure one or more configurable elements of the device to implement a desired design and includes soft data for use by a processor embedded within the device. For one embodiment, control logic is provided to selectively wait for a predetermined time period before processing a next data set.

Growing community of inventors

Mountain View, CA, United States of America

Neil G Jacobson