3dlabs Inc., Ltd.

Du Pont Pixel Systems Limited

E.i. Dupont De Nemours and Company

Neil F Trevett

Malcolm E Wilson

John W Neave

David Robert Baldwin

Andrew Peter Maund

Simon James Moore

David Joseph Salkild, Heir

Iain Stuart MacNaughton

Sarah E Lloyd

Jonathan David Salkild, Deceased

A computer system having a pixel processing unit with multiple subprocessors receives positional data defining graphical objects from the CPU and writes pixel data into the image memory, and a display driver produces an image which partially includes the rendered pixels. The pixel processor is used to access patches of multiple contiguous pixels at a time, and process them in parallel. The patches used are defined, within the overall geometry of the image, to have aligned corners. The unit is also connected to receive synchronization signals from the display driver, conditioned on whether the current line being accessed by the driver is within a specified range of lines in the image space. The unit is operable to command the pixel processing unit to write pixel data corresponding to all pixels covered by a polygon, and in response traverses portions of the image space by scanning portions of one row of patches of pixels at a time, and for some of the patches, testing only the pixels at the leading edge of the patch in the direction of scanning.

Computer system with improved pixel processing capabilities

In a demand-paged virtual memory system, the pages are arranged in the virtual memory space in groups. In order to translate an address from the virtual address space to a physical memory address space, the virtual group address component is input to a contents addressable memory (767), which outputs a group code (767), and the group code and virtual page address component (768X,Y) are input to a RAM page table (750) which outputs the page address. When the physical memory capacity is substantially smaller than the virtual address space, the CAM provides a large saving in page table size. In the case where the data-elements provide a plural-dimensional representation, for example as in pixel data, the pages include data elements which are contiguous in each of the plural dimensions in order to reduce the amount of page-swapping between the physical memory and a paging memory. The data-elements in the physical memory are accessible in parallel as contiguous patches. In order to allow parallel access of patches which are not aligned with respect to a page and therefore may fall partly on the edge of one page and partly on the edge of a page which is contiguous with the first page in the virtual memory but not in the physical memory, the addressing system determines whether a patch to be accessed has data-elements in different pages, and may then modify the addresses to the physical memory.

Virtual memory system

A data processing and memory system for transferring data elements page-by-page between several memories and modifying the data elements in the first memory. In order to reduce the set-up time when generating a new image, the processor stores the background color of the image for each new page. Then, when each new page is transferred to one of the memories, the background color is repeated for each data-element in the page.

Data processing and memory systems with retained background color

A data-array processing system with a memory for storing an array of data-elements, a processor to perform a series of operations on data elements stored in a first section (832) of the memory and to copy data from the first section to a second section (830) of the memory after each series of operations, and output hardware, such a video processor and monitor, for outputting the data-elements in the second section. In order to reduce unnecessary copying of data-elements from the first section to the second section, the processor sets flags indicative of each of the of portions (e.g. P, Q, R, S) of the first section which is modified during that processing operation, and checks the flags during the subsequent copying operation to copy only the flagged portions.

Data-array processing system

A data array processing system comprises a memory system for storing an array of data elements and addressable by a single address, a plural number N of processors (PROC(0)-(15)) capable of processing data elements in parallel, and an address bus. In order to allow parallel access to the memory system where possible, but permit the processors also to access different addresses, each processor is selectable to supply its respective required address (xq, yq) via the address bus to the memory system to access the memory, and each non-selected processor is operable to determine whether it requires access to the address (xq, yq) on the bus, and if so to access the memory system at the same time as the selected processor.

Data-array processing system wherein parallel processors access to the

In a 2-D graphics rendering system having a plurality of processors (PROC 0 to PROC 3) which receive instructions from a common instruction register (IR) and render polygons in a framestore (FS), in order to permit asynchronous performance of the instructions and yet ensure that overlapping polygons are properly rendered, each instruction includes an ordering code, and before writing a pixel to the framestore (FS) each processor checks that the ordering code of the polygon it is rendering is more significant than an ordering code for that pixel stored in an ordering buffer in which case the pixel is written to the framestore (FS) and the order buffer (OB) is updated, but if not the pixel is not written.

Graphics rendering systems

A system and method stores fonts and generates characters. Instead of the fonts containing bit maps, the storage area (116) for each character contains the addresses (GPCR Addresses) of instructions to be used to form the character, and the required parameters for those instructions. In a preferred embodiment, a lookup table (114) for the font contains, for each character, the address of the code to start executing and details of how much more information is stored for this character and where to find it. For each character, the stored information includes addresses of microcode instructions (126) followed by the required number of parameters to define the actions necessary for character generation.

Character generation using graphical primitives

The present invention is a system architecture and methods of operation which reaps all the advantages of patch access processing while allowing many important types of image manipulation to be performed to the granularity and addressability of a single pixel. It goes beyond conventional concepts of the limits of pixel granularity by manipulating pixel data across and within bit planes in a manner which enables bit positions to be exchanged within the same pixel and/or swapped between different pixels.

Raster operations

A system and method of merging and manipulating pixel information for display on a raster scan monitor is disclosed. The invention operates at speeds imperceptible to the viewer by collecting, in each memory access cycle, the data representing multiple pixels and by performing merge and manipulation functions on pixel groups at video rate under control of control data from a state machine. The state machine allows for unique processing decisions to be made for every pixel group displayed on the monitor.

State machine controlled video processor

A multiprocessor subsystem, wherein each processor is separately microcoded so that the processors can run concurrently and asynchronously. To conserve lines and provide flexibility in specifying the subsystem configuration, a serial loop interface preferably provides the data access from the higher-level processor to all of the control stores. To maximize the net bandwidth of this loop, each separate control store preferably interfaces to this serial line using a bank of serial/parallel registers which can load the instructions into the control store, or clock the instruction stream incrementally, or simply clock the instruction stream along as fast as possible. Thus, the bandwidth of this line is used efficiently, and only a minimal number of instructions is required to access control storage for a given processor. One of the processors is a numeric processing module, which is connected to a cache memory by a very wide cache bus. This processor can receive programs either over the serial loop or over the cache bus. The use of the wide cache bus for parallel microinstruction transfer permits fast microcode overlaying. This system even makes dynamic paging of microcode practical in some applications.

Architectures for serial or parallel loading of writable control store

A crossbar converter to format 32 bit raster formatted I/O data into 5.times.4 patch formatted eight bit pixel data enables a 160 bit wide pixel data bus to be used so as to attain a high bandwidth for I/O devices. By using the wide pixel data bus and patch format for I/O, the facilities of the an screen memory and an arbitrary shape clipper can be made available to process a real time video window on a high resolution, bit mapped display monitor. The crossbar converter can be used to convert the parallel input of standard I/O devices into patch format, (five by four by eight, for example). The thus converted I/O data may be used by an off screen memory and an arbitrary shape clipper at high transfer rates.

Crossbar converter

A system and method for merging two or more analog video signals under control of a third analog video signal. A standard video output from one processor's video signal digital to analog converter (DAC) is used as the control signal for the merging of two or more other video signals. This enables the video outputs of even highly diverse processing schemes to be easily merged. In its preferred embodiment, the system includes analog switching circuitry which is used to mix the video outputs from two or more different systems. The system also includes circuitry which converts the standard video output from a third processor into a large swing TTL signal which is used to control the analog switch.

Growing community of inventors

Kingston-upon-Thames, United Kingdom

Neil F Trevett